Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation

Mu-Chi Chen, Yu-Hung Kao, Po-Hsuan Huang, Shao-Chun Ho, Hsiang-Yu Tsou, I-Ting Wu, En-Ming Huang, Yu-Kai Hung, Wei-Po Hsin, Cheng Liang, Chia-Heng Tu, Shih-Hao Hung, H. T. Kung

TL;DR

A unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling.

Abstract

Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.

SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation

TL;DR

A unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling.

Abstract

Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.
Paper Structure (22 sections, 3 equations, 4 figures, 7 tables)

This paper contains 22 sections, 3 equations, 4 figures, 7 tables.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Verilog and Testbench
  4. Training LLMs for Verilog Generation
  5. Verilog Generation with Trained Reasoning Models
  6. Multi-Agent Inference Systems for Verilog Generation
  7. Motivation
  8. Framework Architecture
  9. Training Code Generation
  10. Self-Correction
  11. Model Training Methodology
  12. SFT for SiliconMind-dev Models
  13. SFT for SiliconMind-V1 Models
  14. Inference Strategies
  15. Evaluation
  16. ...and 7 more sections

Figures (4)

  • Figure 1: SiliconMind Framework Overview
  • Figure 2: Training Data Pipeline Overview
  • Figure 3: SiliconMind Inference Engine
  • Figure 4: Pass@1 Performance (%) vs. Average Token Cost Trade-off