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Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

The Verkor Team, Ravi Krishna, Suresh Krishna, David Chin

TL;DR

The methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools are described.

Abstract

Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC.

Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

TL;DR

The methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools are described.

Abstract

Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC.
Paper Structure (24 sections, 5 figures, 1 table)

This paper contains 24 sections, 5 figures, 1 table.

Table of Contents

  1. Introduction
  2. Design Conductor Architecture
  3. Key Capabilities
  4. Stable Long-horizon Execution
  5. Context Management
  6. Technical Mastery
  7. Correctness & Verification
  8. Balancing Exploration & Speed
  9. End-to-end operation
  10. Infra
  11. Architecture
  12. Method
  13. Inputs to DC
  14. Steps followed by DC
  15. Results
  16. ...and 9 more sections

Figures (5)

  • Figure 1: GDSII plots of VerCore designs (70µm $\times$ 70µm)
  • Figure 2: High-level overview of Design Conductor's Architecture
  • Figure 3: Typical design process of Design Conductor. Note that for VerCore, there is no "legacy design".
  • Figure 4: VerCore pipeline diagram.
  • Figure 5: An illustration of how teams might restructure to make the most effective use of DC. Many more designs and product ideas would be explored by a number of sub-teams, each capable of producing a single design from start to finish.