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A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction

Supriyo Bandyopadhyay

Abstract

The XOR Boolean logic gate is widely used in many applications such as encryption (XOR ciphers), binary addition (half- and full-adders), error detection (parity bits), etc. but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results in a large gate footprint and low logic density. Here, we present the design of an XOR gate with a single straintronic magnetic tunnel junction which reduces the footprint dramatically. Such a gate is non-volatile and hence suitable for non-von-Neumann architectures, processor-in-memory, etc. The switching time of the gate is ~200 ps and the energy dissipation per gate operation is ~225 aJ. Cascading of successive stages is accomplished via a CMOS device which plays no role in the gate dynamics but is needed for gain to provide logic level restoration, fan-out and isolation between input and output. This 1 MTJ-1 CMOS design has an energy dissipation that is an order of magnitude smaller than what has been reported for traditional all-transistor XOR designs.

A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction

Abstract

The XOR Boolean logic gate is widely used in many applications such as encryption (XOR ciphers), binary addition (half- and full-adders), error detection (parity bits), etc. but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results in a large gate footprint and low logic density. Here, we present the design of an XOR gate with a single straintronic magnetic tunnel junction which reduces the footprint dramatically. Such a gate is non-volatile and hence suitable for non-von-Neumann architectures, processor-in-memory, etc. The switching time of the gate is ~200 ps and the energy dissipation per gate operation is ~225 aJ. Cascading of successive stages is accomplished via a CMOS device which plays no role in the gate dynamics but is needed for gain to provide logic level restoration, fan-out and isolation between input and output. This 1 MTJ-1 CMOS design has an energy dissipation that is an order of magnitude smaller than what has been reported for traditional all-transistor XOR designs.
Paper Structure (11 sections, 1 equation, 5 figures, 2 tables)

This paper contains 11 sections, 1 equation, 5 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Gate Design
  3. Gate dynamics
  4. XOR functionality
  5. Appendix
  6. Standby power dissipation
  7. Stability of $\phi$
  8. Switching speed
  9. Energy dissipation
  10. Concatenation, cascading, fan-out and logic restoration
  11. Conclusion

Figures (5)

  • Figure 1: The net effective magnetic field in the elliptical magnetostrictive soft layer of a magnetic tunnel junction subjected to an external magnetic field and uniaxial strain along the major axis. The angle subtended by the net magnetic field with the major axis of the soft layer is $\phi$. The easy axis of the hard layer subtends an angle $\theta$ with its own major axis.
  • Figure 2: Design of an XOR gate with a single straintronic MTJ. The two inputs are encoded in the currents $I_1$ and $I_2$, whereas the output is encoded in the voltage $V_{out}$.
  • Figure 3: Schematic representation of the resistance of the MTJ as a function of the strain-induced rotation angle $\phi$.
  • Figure 4: (a) The potential well surrounding the critical angle. (b) The fluctuation in the critical angle due to thermal noise at room temperature is a mere $\sim$ 0.2 degrees. Reproduced from rahnuma with permission of the IEEE.
  • Figure 5: The concatenation scheme for providing gain for logic level restoration and fan-out.