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NL2GDS: LLM-aided interface for Open Source Chip Design

Max Eland, Jeyan Thiyagalingam, Dinesh Pamunuwa, Roshan Weerasekera

TL;DR

NL2GDS (Natural Language to Layout), a novel framework that leverages large language models to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow, is introduced.

Abstract

The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.

NL2GDS: LLM-aided interface for Open Source Chip Design

TL;DR

NL2GDS (Natural Language to Layout), a novel framework that leverages large language models to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow, is introduced.

Abstract

The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.
Paper Structure (20 sections, 5 equations, 6 figures, 3 tables)

This paper contains 20 sections, 5 equations, 6 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Related Work and Motivation
  3. LLM-Based HDL Generation
  4. End-to-End EDA Flow Orchestration
  5. Motivation and Our Contribution
  6. System Overview
  7. Web Based Front End
  8. Agentic Approach
  9. Retrieval Augmented Generation
  10. Cloud Backend
  11. Implementation
  12. Chain of Thought
  13. RAG in the NL2GDS Flow
  14. Parallelism
  15. Evaluation
  16. ...and 5 more sections

Figures (6)

  • Figure 1: NL2GDS Flow
  • Figure 2: NL2GDS Block Diagram
  • Figure 3: NL2GDS Front End Initial Prompt
  • Figure 4: Comparison of NL2GDS Vs ISCAS for Area, Delay and Power Metrics
  • Figure 5: Layouts generated for a 16×16 combinational multiplier in OpenROAD using (a) ISCAS input (chip size: 192.89um × 193.665um) and (b) NL2GDS-generated Verilog code (167.34um × 165.96um).
  • ...and 1 more figures