SpiderCat: Optimal Fault-Tolerant Cat State Preparation

TL;DR

This paper constructively finds optimal circuits for CAT states in a more scalable way by encoding the construction of optimal graphs as a constraint satisfaction problem and constructing explicit constructions for circuits that match this lower bound on CNOT count.

Abstract

The ability to fault-tolerantly prepare CAT states, also known as multi-qubit GHZ states, is an important primitive for quantum error correction. It is required for Shor-style syndrome extraction, and can also be used as a subroutine for doing fault-tolerant state preparation of CSS codewords. Existing approaches to fault-tolerant CAT state preparations have been found using computationally expensive heuristics involving SAT solving, reinforcement learning, or exhaustive analysis. In this paper, we constructively find optimal circuits for CAT states in a more scalable way. In particular, we derive formal lower bounds on the number of CNOT gates required for circuits implementing $n$-qubit CAT states that do not spread errors of weight at most $t$ for $1\leq t \leq 5$. We do this by using fault-equivalent rewrites of ZX-diagrams to reduce it to a problem of characterising certain 3-regular simple graphs. We then provide families of such optimal graphs for infinitely many values of $n$ and $t\leq5$. By encoding the construction of optimal graphs as a constraint satisfaction problem we find explicit constructions for circuits that match this lower bound on CNOT count for all $n\leq50$ and $t \leq 5$ and for nearly all pairs $(n,t)$ with $n\leq 100$ and $t\leq 5$ or $n\leq 50$ and $t\leq 7$, significantly extending the regimes that were achievable by previous methods and improving the resource counts for existing constructions. We additionally show how to trade CNOT count against depth, allowing us to construct constant-depth fault-tolerant implementations using $O(n)$ ancilla and $O(n)$ CNOT gates.

Figures (21)

• Figure 1: Mapping basic quantum states, Pauli operators, and Pauli measurements to Pauli ZX-diagrams, $n\in \mathbb{N}\xspace$ and $k \in \{0,1\}$. As we note in the next section, the direction of wires is irrelevant, so we can write CNOT gates using vertical wires between spiders without ambiguity. These equalities hold up to some known scalar factor, which is not relevant in this paper.
• Figure 2: An example of a diagram with a possible fault.
• Figure 3: A collection of fault-equivalent rewrite rules that are useful for fault-tolerant CAT-state preparation. Here $w,n \in \mathbb{N}\xspace$ and $w \leq n$.
• Figure 4: Example of a $t$-FT preparation of a $16$-qubit CAT state for $t\in\{1,3\}$. On the left there are enough free qubits to parallelise the $ZZ$-measurements, while on the right multiple layers are needed. Coloured lines represent the individual layers of $ZZ$-measurements coming from \ref{['fig:fe-rewrites']}.
• Figure 5: An example of a Z-graph, its underlying graph, and its underlying marked graph.

Theorems & Definitions (71)

• Definition 2.1
• Remark 2.1
• Definition 2.2: Faults locations, faults
• Proposition 2.1: Detectability of Faults, rodatz2025fault
• Proposition 2.2
• Definition 2.3: Fault equivalence, $w$-fault equivalence
• Definition 2.4: Fault-tolerant CAT-state preparation
• Theorem 3.1
• Definition 4.1
• Lemma 4.1