A Fully Open-source Implementation of an Analog 8-PAM Demapper for High-speed Communications

TL;DR

This paper design and simulate an analog 8-ary pulse-amplitude modulation (8-PAM) demapper in IHP SG13G2 SiGe BiCMOS technology and generalize and improve a design available in the literature for 4-PAM, and proposes a fully MOSFET-based 8-PAM design.

Abstract

Spectrally-efficient communication systems rely on the use of multi-level modulation formats. At the receiver side, a demodulator is often used to extract soft information about the transmitted bits. Such a demodulator is typically implemented in the digital domain. However, analog implementations of such demodulators are also possible. In this paper, we design and simulate an analog 8-ary pulse-amplitude modulation (8-PAM) demapper in IHP SG13G2 SiGe BiCMOS technology. We generalize and improve a design available in the literature for 4-PAM. A fully MOSFET-based 8-PAM design is proposed. Our simulations and design are completely based on open-source IC design tools. Our results show an energy efficiency of 0.33 pJ/bit for a data rate of 1Gbit/s.

Figures (6)

• Figure 1: System model of the considered 8-PAM transmission. Bits $b_{1},b_{2},b_{3}$ are mapped to constellation symbols, transmitted over the channel, and converted into LLRs $L_{1},L_{2},L_{3}$ by the demapper. The r.h.s. of this figure shows the simulation model used for the proposed analog implementation of the demapper.
• Figure 2: LLRs for bit positions $k=1$ (top), $k=2$ (middle), and $k=3$ (bottom) at $\text{SNR}=10~dB$. The received symbol $r$ is scaled by $(\alpha,\beta)$ to obtain $V_{\text{in}}$. The scaled constellation points are also shown. The analog demapper output voltages $V_{\text{out}}$ are scaled by $(\gamma_k,\zeta_k)$ to obtain the LLRs.
• Figure 3: Single cell implementing one segment of the piece-wise linear LLR function. The inset shows the transfer characteristics for the original design seguin_2004 (BJTs) and our proposed architecture (MOSFETs).
• Figure 4: Rate penalty relative to the digital exact demapper vs SNR of the max-log, BJT and MOSFET approximations
• Figure 5: BER performance over sampling frequency. The horizontal lines indicate the reference BER from hard decisions on LLRs from the digital exact demapper at $\text{SNR}=10~dB$, representing the best achievable performance.