Dissipation-Reliability Tradeoff for Stochastic CMOS Bits in Series

Abstract

Physical instantiations of a bit of information are subject to thermal noise that can trigger unintended bit-flip errors. Bits implemented with CMOS technology typically operate in regimes that reliably suppress these errors with a large bias voltage, but miniaturization and circuit design for implantable biomedical devices motivate error suppression via alternative low-voltage strategies. We present and analyze an error-suppression technique that involves coupling multiple CMOS units into chains, introducing a natural error correction arising from inter-unit correlations. Using tensor networks to numerically solve a stochastic master equation for the CMOS chain, we quantify the reliability-dissipation tradeoff across system sizes that would be intractable with conventional sparse-matrix methods. The calculations show that the typical time for bit-flip errors scales exponentially with the bias voltage but subexponentially with the chain length. While a CMOS chain adds stability compared to a single CMOS unit for a fixed low bias voltage, increasing the bias voltage is a lower-dissipation route to equivalent stability.

Figures (3)

• Figure 1: The minimal instantiation of a bit with CMOS technology is a single unit with two nodes at voltages $v_0$ and $v_1$. These nodes are coupled by two NOT gates, each consisting of an n-type ($-$) and p-type ($+$) transistor. In all four transistors, electrons hop in both directions between ideal thermodynamic reservoirs ($-V_{\rm dd}$ and $V_{\rm dd}$) and the fluctuating voltage nodes. Rates for those hops, $\lambda$, depend on $\mathbf{v}$, with three indices indicating the NOT gate, the n/p transistor, and the direction of the hop. The coupled nodes yield a bistable steady state (right), with each peak corresponding to a metastable bit-state.
• Figure 2: The rate operator, Eq. \ref{['eq:rateoperator']}, can be compressed into a matrix product operator (MPO), shown in blue. Right eigenvectors of the single-CMOS-unit problem are used as basis vectors $\phi_i$, and DMRG is used to find controllable approximations for the top two right eigenvectors of the $L$-unit problem.
• Figure 3: Reliability vs. dissipation tradeoff for CMOS chains. The mean time between bit-flip errors $\langle\tau_{\rm err}\rangle$ (left) increases exponentially with bias voltage $V_{\rm dd}$ but subexponentially with chain length $L$. Steady-state dissipation $\dot{Q}$ (right) scales linearly with both $V_{\rm dd}$ and $L$. Consequently, for any fixed dissipation budget (horizontal line), maximum reliability is achieved with minimum $L$ and maximum $V_{\rm dd}$. Both quantities normalized by the characteristic circuit timescale $\tau_0=\frac{e}{I_0}e^{V_{\rm th}/(nV_T)}$, where $I_0$ is the specific current of the transistor.