Fault-tolerant execution of error-corrected quantum algorithms

TL;DR

This work demonstrates near-break-even performance of complex, error-corrected algorithmic quantum circuits using only fault-tolerant components, and shows that adding active QEC cycles and increasing the repeat-until-success limit of state preparation subroutines can improve the performance of a quantum algorithm.

Abstract

Scaling up quantum algorithms to tackle high-impact problems in science and industry requires quantum error correction and fault tolerance. While progress has been made in experimentally realizing error-corrected primitives, the end-to-end execution of logical quantum algorithms using only fault-tolerant (FT) components has remained out of reach. We demonstrate the FT and error-corrected execution of two quantum algorithms, the Quantum Approximate Optimization Algorithm (QAOA) and the Harrow-Hassidim-Lloyd (HHL) algorithm applied to the Poisson equation, on Quantinuum H2 and Helios trapped-ion quantum processors using the $[[7,1,3]]$ Steane code. For QAOA circuits on 5 and 6 logical qubits, we show performance improvements from increasing the number of QAOA layers and the number of $T$ gates used to approximate logical rotations, despite increased physical circuit complexity. We further show that QAOA circuits with up to 8 logical qubits and 9 logical $T$ gates perform similarly to unencoded circuits. For the largest QAOA circuits we run, with 12 logical (97 physical) qubits and 2132 physical two-qubit gates, we still observe better-than-random performance. Finally, we show that adding active QEC cycles and increasing the repeat-until-success limit of state preparation subroutines can improve the performance of a quantum algorithm, thereby demonstrating critical capabilities of scalable FT quantum computation. Our results are enabled by an FT logical $T$ gate implementation with an infidelity of $\sim 2.6(4)\times10^{-3}$ and dynamic circuits with measurement-dependent feedback. Our work demonstrates near-break-even performance of complex, error-corrected algorithmic quantum circuits using only FT components.

Figures (22)

• Figure 1: A geometric representation of the Steane code. Nodes represent qubits. Colored cells identify stabilizer group generators, which are obtained by taking the product of either Pauli-$X$ or Pauli-$Z$ operators on the adjacent nodes, such as $X_1 X_2 X_6 X_5$. The product of either Pauli-$X$ or Pauli-$Z$ operators on any exterior edge of the triangle yields, respectively, a logical Pauli-$X$ or Pauli-$Z$ operator, such as $Z_0 Z_4 Z_3$.
• Figure 2: Repeat-until-success protocol to fault-tolerantly prepare a logical $\ket{\overline{0}}$ state of the Steane code using CNOT and CZ gates. The bottom qubit is an ancilla ("flag") qubit that is physically measured in the $X$ basis to read out the value of the logical $\overline{Z} \simeq Z_1 Z_3 Z_5$ operator. This protocol "succeeds" if the flag measurement outcome is 0 (that is, if the flag qubit is found to be in $\ket{+}$ upon measurement in the $X$ basis); otherwise, the qubits in this circuit are reset and the protocol is repeated until success.
• Figure 3: Repeat-until-success protocols to fault-tolerantly prepare $\ket{\overline{H}}$. Measurements are performed in the $Z$ or $X$ basis as indicated. \ref{['fig:prep_h_old']} A circuit that non-fault-tolerantly encodes a single-qubit $\ket{H}$ state into $\ket{\overline{H}}$, fault-tolerantly measures $\overline{H}$, and runs a full round of QED that consists of six stabilizer measurements. \ref{['fig:prep_h_new']} A specialized circuit to fault-tolerantly prepare $\ket{\overline{H}}$ using a shorter non-fault-tolerant $\ket{\overline{H}}$ preparation circuit, two qubits to flag mid-circuit errors, a fault-tolerant measurement of $\overline{H}$, and two stabilizer measurements. Here $R_{XX}(\theta) = e^{-i\theta X\otimes X/2}$ is a two-qubit Pauli rotation on the qubits indicated by dots ($\bullet$). The circuit here has been expanded for clarity, but can be implemented with a two-qubit gate depth of 9.
• Figure 4: \ref{['fig:t_gate_bare']},\ref{['fig:t_gate_swap']}: Two gadgets that consume a $\ket{T} = T\ket{+}$ state to apply a $T$ gate to an arbitrary single-qubit state $\ket\psi$. At the level of circuit identities, these gadgets can be generalized by replacing $T\to R_Z(\theta)$ and $S\to R_Z(2\theta)$ for any angle $\theta$, but the resulting circuits may not have fault-tolerant implementations. \ref{['fig:qec_steane_bare']},\ref{['fig:qec_steane_swap']}: Analogous gadgets (with $\theta=0$) that implement a fault-tolerant error detection cycle for bit-flip ($X$) errors. For \ref{['fig:qec_steane_bare']}, detected errors can be either actively corrected or tracked in software. For \ref{['fig:qec_steane_swap']}, the conditional logical $\overline{X}$ correction can similarly be tracked in software by updating a Pauli frame. Gadgets \ref{['fig:t_gate_swap']} and \ref{['fig:qec_steane_swap']} have the benefit of mitigating leakage errors in $\ket\psi$ and correcting physical $X$ errors passively, as these errors do not propagate to the output state of the gadget. Changing bases as $Z\leftrightarrow X$, $\ket+\leftrightarrow\ket0$, and flipping the orientation of the CNOT yields gadgets for fault-tolerantly implementing a $T_X = HTH$ gate and detecting phase-flip errors.
• Figure 5: Non-fault-tolerant gadget to measure the Pauli string $X_0 Y_1 Z_2$, writing the result to the bit $m$. Single-qubit errors in the middle of the decomposition on the right can propagate to higher-weight errors on qubits $q_0,q_1,q_2$.

Theorems & Definitions (6)

• Lemma 1
• proof
• Lemma 2
• proof
• Lemma 3
• proof