Demonstrating Noise-adapted Quantum Error Correction With Break-Even Performance

TL;DR

This work uses a recently developed noise-adapted 3-qubit QEC scheme to demonstrate break-even performance against native amplitude-damping noise on IBM quantum hardware, and defines a measure of gain, that allows for faithful performance benchmarking of the protocol.

Abstract

The promise of quantum computing is closer to reality today than ever before, thanks to rapid progress in the development of quantum hardware. Even as qubit lifetimes and gate fidelities continue to improve, realizing robust, fault-tolerant quantum computers is contingent upon the successful implementation of quantum error correction (QEC). Conventional QEC schemes have rather high resource overheads and low threshold requirements, making them challenging to implement on present day hardware. Here, we use a recently developed noise-adapted 3-qubit QEC scheme to demonstrate break-even performance against native amplitude-damping (AD) noise on IBM quantum hardware. We use variational quantum circuits to construct hardware-efficient encoding and decoding circuits. This scheme is probabilistic due to the non-unitary nature of the recovery operators, which are implemented via the block-encoding technique. We demonstrate logical qubit lifetimes exceeding those of the physical qubits by performing multiple rounds of QEC. To further protect the qubits from dephasing due to crosstalk, we incorporate dynamical decoupling into our noise-adapted QEC scheme in a seamless fashion. To account for the post-selection overhead, we define a measure of gain, that allows for faithful performance benchmarking of the protocol. Our analysis suggests that the performance of our protocol is limited primarily by the measurement readout fidelity, and is bound to improve with successive generations of quantum processors.

Figures (10)

• Figure 1: (a) Schematic circuit for multi-cycle QEC. The unitary $G$ and the encoder ($\textrm{En}$) prepare an arbitrary logical state, that undergoes both damping and dephasing during the free evolution (Delay). Syndrome extraction and recovery each require an additional ancilla. The delay & QEC block is repeated for $n$ rounds, resetting the ancilla each time. Finally, $(\textrm{En})^{\dagger}$ and $G^{\dagger}$ are applied, followed by a measurement to estimate the fidelity. (b) Fidelity of the physical and logical qubits as a function of time. The total evolution time is the sum of the delay and QEC protocol runtimes. The grey line (background) is the average $T_{1}$ ($T_{1}$ spread). The green (blue) line is for $\ket{0_{L}}$ ($\ket{1_{L}}$). Multi-QEC is plotted for $\ket{1_{L}}$ with maximum allowed delays of $30 \mu s$ and $50 \mu s$ between consecutive QEC cycles.
• Figure 2: The multi-QEC circuit design. (a) VQC and circuit design process flowchart. We approximate the recovery by fixing $\gamma = 0$. We use an ansatz and run a classical optimization routine to find the optimal hardware-efficient circuit decomposition. (b) The encoder circuit. The ansatz for all our QEC components has a similar structure as seen in the decomposed encoding circuit. $R_X(\theta)$ is denoted in orange, and $R_Z(\theta)$ in peach. The displayed value in the box $\eta$ represents the optimized rotational angle as multiples of $\pi$. (c) The recovery circuit. The syndrome measurement circuit ends before the $X$ gate in the subfigure. The explicit circuits are given in the Appendix \ref{['sec: appB']}. (d) Approximate recovery performance. The plot shows the simulated fidelity obtained with the approximate recovery, under $T_{1}$, $T_{2}$, gate, and readout noise. The grey dots give the average $T_{1}$. The light (dark) green (blue) points show the performance of the single (multi) QEC for $\ket{0_{L}}$ ($\ket{1_{L}}$).
• Figure 3: Layout of the IBM Torino device. Data qubits forming the logical qubit are shown in blue, ancilla qubits used for syndrome extraction and post-selection in green, and spectator qubits (nearest neighbour of the data qubits and the ancilla qubits) participating in the CHaDD sequence in orange. Idle qubits are marked in gray.
• Figure 4: Hardware experiment results of multi-QEC on IBM Torino. Top three figures (a), (b), (c) show the multi-QEC logical qubit fidelity for the $\ket{0_{L}}$ and $\ket{1_{L}}$ states in comparison with the bare qubit. The grey dots (background) represent the average $T_{1}$ ($T_{1}$ spread) of the bare qubits of that set. The green (blue) squares (diamonds) emphasize the logical $\ket{0_{L}}$ ($\ket{1_{L}}$) fidelity. Bottom three figures (d), (e), (f) show the multi-QEC logical qubit fidelity for the $\ket{+_{L}}$ state in comparison with the bare qubit, both with and without the CHaDD protocol. The grey dots (background) represent the average $T_{1}$ ($T_{1}$ spread) of the bare qubits of that set. The maroon (orange) pentagons (hexagons) show the fidelity of the logical $\ket{+_{L}}$ without CHaDD (with CHaDD).
• Figure 5: Analyzing the effect of CHaDD on logical qubits. a) Toy model simulation. A toy $2$-qubit model, with $ZZ$ crosstalk interaction, with populations of $\ket{0}$ (green) and $\ket{1}$ (blue) of the probe qubit is shown. The solid line shows the populations with the application of the CHaDD protocol. b) ChaDD executed during multi-QEC for the codewords. Shows the effect of CHaDD on the logical qubit's $\ket{0_{L}}$ and $\ket{1_{L}}$ populations averaged over the same $3$ qubit sets considered previously. The background shaded area is the standard deviation across the different sets.

Theorems & Definitions (2)

• Lemma 1: State Fidelity
• proof