CarbonPATH: Carbon-aware pathfinding and architecture optimization for chiplet-based AI systems

TL;DR

CarbonPATH is an early-stage pathfinding framework that identifies optimized HI systems by co-designing workload mapping, architectural parameters, and packaging technologies, while treating sustainability as a first-class design constraint.

Abstract

The exponential growth of AI has created unprecedented demand for computational resources, pushing chip designs to the limit while simultaneously escalating the environmental footprint of computing. As the industry transitions toward heterogeneous integration (HI) to address the yield and cost challenges of monolithic scaling, minimizing the carbon cost of these complex HI systems becomes critical. To fully exploit HI, a co-design approach spanning application, architecture, chip, and packaging is essential. However, this creates a vast design space with competing objectives, specifically the trade-offs between performance, cost, and carbon footprint (CFP) for sustainability. CarbonPATH is an early-stage pathfinding framework designed to address this multi-objective challenge. It identifies optimized HI systems by co-designing workload mapping, architectural parameters, and packaging technologies, while treating sustainability as a first-class design constraint. The framework accounts for a wide range of factors, including compute and memory sizes, chiplet technology nodes, communication protocols, integration style (2D, 2.5D, 3D), operational CFP, embodied CFP, and interconnect type. Using simulated annealing, CarbonPATH explores this high-dimensional space to identify solutions that balance traditional metrics against environmental impact. By capturing interactions across applications, architectures, chiplets, and packaging, CarbonPATH uncovers system-level solutions that traditional methods often miss due to restrictive assumptions or limited scope.

Figures (15)

• Figure 1: System-level co-design across application, chip architecture, chiplet configuration, and package choices for chiplet-based accelerators.
• Figure 2: Overview of different packaging interconnect architectures (a) RDL fanout, (b) EMIB, (c) TSV and µ Bump, and (d) hybrid bond.
• Figure 3: CarbonPATH framework that leverages SA to identify the best HI system architecture for a given workload and design considerations.
• Figure 4: Example to demonstrate the topology and datapath for latency estimation in 2.5D integration technology.
• Figure 5: Normalized D2D latency for different number of chiplets for WL1 for (a) 2.5D-RDL-DDR5 and 3D-µ B-DDR5 normalized to 2.5D-RDL-DDR5 with 2 chiplets and (b) 2.5D-RDL-HBM3 and 3D-HB-HBM3 packaging and memory configurations normalized to 2.5D-RDL-HBM3 with 2 chiplets.