Variational Gibbs State Preparation on Trapped-Ion Devices

Abstract

We implement a variational quantum algorithm for Gibbs state preparation of a transverse-field Ising model on IonQ's quantum computers. To this end, we train the variational parameters via classical simulation and perform state tomography on the quantum devices to evaluate the fidelity of the prepared Gibbs state. As a main result, we find that fidelity decreases (non-monotonically) as a function of the inverse temperature $β$ of the system. Fidelity also decreases as a function of the size of the system. Interestingly, we find that a Gibbs state prepared for a specified $β$ is a better representative of a Gibbs state prepared for a $\textit{lower}$ $β$; or in other words, thermal fluctuations in the quantum hardware lead to digital heating, that is, an increase in the temperature of the prepared Gibbs state above what was intended.

Figures (10)

• Figure 1: An overview of $U_G(\boldsymbol\theta,\boldsymbol\phi)$, the parametrized quantum algorithm for Gibbs state preparation. This algorithm acts on two $n$-qubit quantum registers, an ancilla register $A$ and a system register $S$. The algorithm consists of two unitaries: $U_A(\boldsymbol\theta)$, which acts on the ancilla register, and $U_S(\boldsymbol\phi)$, which acts on the system register. Between these two unitaries, a layer of CNOT gates is applied transversely between the registers.
• Figure 2: The details of $U_A(\boldsymbol\theta)$ (see Fig. \ref{['fig:alg-overview']}), the state-preparation unitary for the ancilla register. This unitary consists of two columns of $R_y(\theta_i)$ gates for $i\in[1,n]$, separated by a layer of CNOT gates acting between adjacent qubits $a_i$ and $a_{i+1}$ for $i\in[1,n-1]$. The gates within the dashed box constitute one ancilla layer. In general, one can perform an arbitrary number of ancilla layers. In this paper, we consistently use one ancilla layer in all experiments.
• Figure 3: The implementation of the $U_S(\boldsymbol\phi)$ of Fig. \ref{['fig:alg-overview']}. This operation consists of the application of an $R_p(\theta_{2i-1},\theta_{2i})$ gate to qubits $s_i$, $s_{i+1}$ (where $s_{n+1}=s_1$) for $i\in[1,n]$. For the implementation of the $R_p(\theta_{2i-1},\theta_{2i})$ gate, see Fig. \ref{['fig:alg-rp']}. The collection of $n$$R_p(\theta_{2i-1},\theta_{2i})$ gates constitutes a system layer. In general, multiple system layers can be performed within $U_G(\boldsymbol\theta,\boldsymbol\phi)$; in this paper, we consistently use one system layer.
• Figure 4: The definition of the $R_p(\phi_{2i-1},\phi_{2i})$ gate. Note that this gate operates on qubits $s_i$ and $s_{i+1}$. Moreover, this is an abstract representation of the operation; for execution on hardware, this must be transpiled into hardware native gates. For more on hardware native gates, see Appendix \ref{['sec:hardware']}.
• Figure 5: The number of one- and two-qubit native gates required to implement the GSP algorithm on both IBM hardware and IonQ hardware. All native-gate circuits were generated using the Qiskit transpiler, targeting the Brisbane and Aria backends from IBM and IonQ, respectively. Note that while the number of one-qubit gates scales more rapidly on IonQ hardware, the opposite is true for two-qubit gates. Since the dominant source of gate error arises from two-qubit gates, it follows that the IonQ hardware potentially outperforms the IBM hardware in terms of algorithm fidelity.