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TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference

Mhd Rashed Al Koutayni, Mohamed Selim, Gerd Reis, Alain Pagani, Didier Stricker

TL;DR

TinyIceNet is presented, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.

Abstract

Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.

TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference

TL;DR

TinyIceNet is presented, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.

Abstract

Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.
Paper Structure (16 sections, 2 equations, 4 figures, 4 tables)

This paper contains 16 sections, 2 equations, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Dataset and Preprocessing
  4. Proposed Approach
  5. Network Design
  6. Training Protocol
  7. Loss Function and Evaluation Metric
  8. Network Optimization
  9. FPGA Deployment Using High-Level Synthesis
  10. Experiments and Results
  11. Experimental Setup
  12. Accuracy and Quantization Effects
  13. Runtime, Energy Efficiency and FPGA Resource Utilization
  14. Comparison with Related Works
  15. Qualitative Results
  16. ...and 1 more sections

Figures (4)

  • Figure 1: TinyIceNet Network Architecture, consisting of an encoder followed by upsample operation and a tiny segmentation head (Conv $1\times1$ and ArgMax). DConv-3 stands for Double Convolutional layer with a kernel size of $3$, as shown in the bottom left side.
  • Figure 2: Overview of the streaming convolution architecture used in TinyIceNet. Each layer follows a unified pipeline consisting of (1) line-buffered input streaming, (2) parallel MAC compute arrays scaled by input/output unrolling factors, and (3) output streaming. Three variants are supported: standard Conv2D, Conv2D with Serial-In–Parallel-Out (SIPO) multi-output parallelism, and pointwise $1 \times 1$ convolution.
  • Figure 3: Accuracy curve: F1 score as a function of weight bitwidth for Full-Precision, QAT, and PTQ (7--32 bits). The line is drawn to illustrate the accuracy trend although the quantization steps and the corresponding F1 scores are discrete.
  • Figure 4: Qualitative comparison of TinyIceNet predictions. The individual F1 scores for the selected scenes are mentioned besides each inference row.