Table of Contents
Fetching ...

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

Md. Mamunur Rahman, Ensar Vahapoglu, Kok Wai Chan, Tuomo Tanttu, Ajit Dash, Jonathan Yue Huang, Venkatesh Chenniappan, Fay Hudson, Christopher C. Escott, Yik Kheng Lee, Arne Laucht, Andrea Morello, Andre Saraiva, Jared H. Cole, Andrew S. Dzurak, Wee Han Lim

Abstract

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, poly-Si-gated CMOS-foundry devices achieve the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

Abstract

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of AlO markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, poly-Si-gated CMOS-foundry devices achieve the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.
Paper Structure (11 sections, 7 equations, 7 figures)

This paper contains 11 sections, 7 equations, 7 figures.

Figures (7)

  • Figure 1: Hall-bar device structure and peak-mobility comparison as a function of gate-stack engineering at 1.4 K.(a) Schematic illustration of the fabricated Hall-bar device (not drawn to scale), highlighting the top gate, gate-oxide stack, and the n$^{+}$ doped ohmic contact regions. (b) Peak mobility, $\mu_{\mathrm{peak}}$, for SiO$_2$/Al$_2$O$_3$-based gate stacks grown under various Al$_2$O$_3$ deposition conditions. The oxidants (H$_2$O and D$_2$O) and deposition temperatures (200 and 300$^{\circ}$C) were systematically varied to assess their impact on oxide quality and electron mobility. (c) Comparison of peak mobilities from four device configurations incorporating different gate-oxide stacks and gate-metal materials. For SiO$_2$/Al$_2$O$_3$ devices, the highest-mobility condition identified in panel (b) is used for benchmarking. (d) The percolation density, $n_{\mathrm{p}}$, extracted for each device type (corresponding to the mobility data in panel (c)). Devices with lower mobility consistently exhibit higher percolation densities, indicative of increased disorder in the conduction channel. At least two devices were measured per configuration for the data shown in panels (c) and (d). The error bars represent the standard deviation of the measured values across devices within each configuration.
  • Figure 2: Quantum dot device architectures and charge-noise characterization(a) Double quantum dot device fabricated in the UNSW cleanroom using overlapping metal gate electrodes defined by a lift-off process. (b) Double quantum dot device fabricated on a 300 mm wafer at imec using a CMOS-compatible process, employing etched poly-Si gate electrodes. In both schematics, the red gates represent the first-layer gates, the blue gates denote the second-layer gates, and the purple gates correspond to the third-layer gates. The thermally grown SiO$_2$ is shown in white, while the silicon substrate is illustrated in grey. Three quantum dots are formed beneath the ST (named as SET dot), P1, and P2 gates; however, for the analysis presented in panels (c) and (d), only the charge-noise data from the SET are considered. (c) Charge-noise spectra measured from the SET dot of representative devices from the four device types shown in Fig. \ref{['Figure 1_Chargenoise']}(c), with solid curves indicating power-law fits of the form $S_{\mathrm{0}}/f^{\gamma}$. (d) Charge-noise amplitudes extracted at 1 Hz and 4 K for all measured devices, obtained from the power-law fits to the spectra shown in panel (c). For each device category, measurements were performed on at least two nominally identical devices, except for the poly-Si–gated device, where a single device was measured. The error bars represent the standard deviation of the measured values across devices within each configuration.
  • Figure 3: Charge-stability mapping and Dot--SET feedback characterization of quantum dot devices.(a) Charge-stability diagram of the RTF device, identified as the lowest charge-noise performer, plotted as a function of the plunger-gate voltages $V_{\mathrm{P1}}$ and $V_{\mathrm{P2}}$. The horizontal and vertical transition lines correspond to electron loading in the P1 and P2 quantum dots, respectively, down to the last occupied electron. The star symbols mark the transition points where the dot signals are held fixed for operation of the dual-feedback control system. (b) A dual-feedback control scheme is used to stabilize the operating currents of both the SET sensor and the quantum dot by dynamically adjusting their respective gate voltages. The recorded feedback corrections, $\Delta V_{\mathrm{ST}}^{(\mathrm{fb})}$ and $\Delta V_{\mathrm{P}}^{(\mathrm{fb})}$, quantify the electrostatic compensation required to maintain fixed operating points and are converted to energy units using independently calibrated gate lever arms. (c) Comparison of dot--SET feedback stability maps from four representative devices incorporating different high-$\kappa$ oxides and gate-metal stacks, shown for the first-electron transition of the P1 and P2 dots. These were recorded continuously over a three-hour interval. The temporal drift of the operating point is visualized using the associated color scale. A larger spread or distortion of the stability map indicates increased charge instability and a noisier electrostatic environment.
  • Figure 4: Magneto-transport characteristics of Hall-bar devices. Longitudinal resistivity $\rho_{\mathrm{XX}}$ and Hall resistance $R_{\mathrm{XY}}$ measured as functions of magnetic field B at 1.4 K for four Hall-bar devices incorporating different high-$\kappa$ oxides and gate-metal stacks. Inset: Dingle analysis of the Shubnikov--de Haas oscillations used to extract the quantum lifetime $\tau_{\mathrm{q}}$, with the solid line indicating the fit to the oscillation amplitudes.
  • Figure 5: Current-noise spectroscopy of quantum dot devices. Current-noise power spectral densities measured from five representative devices with different oxide stacks and gate metals, fabricated on the UC and RTF platforms. Solid curves show the noise spectra measured at the maximum of the $dI/dV$ transconductance, while dotted curves indicate the baseline noise measured with the devices in the OFF state (no source--drain current), as illustrated in the inset.
  • ...and 2 more figures