Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices
Md. Mamunur Rahman, Ensar Vahapoglu, Kok Wai Chan, Tuomo Tanttu, Ajit Dash, Jonathan Yue Huang, Venkatesh Chenniappan, Fay Hudson, Christopher C. Escott, Yik Kheng Lee, Arne Laucht, Andrea Morello, Andre Saraiva, Jared H. Cole, Andrew S. Dzurak, Wee Han Lim
Abstract
We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, poly-Si-gated CMOS-foundry devices achieve the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.
