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Rate-Fidelity Tradeoffs in All-Photonic and Memory-Equipped Quantum Switches

Panagiotis Promponas, Leonardo Bacciottini, Paul Polakos, Gayane Vardoyan, Don Towsley, Leandros Tassiulas

Abstract

Quantum entanglement switches are a key building block for early quantum networks, and a central design question is whether near-term devices should use only flying photons or also incorporate quantum memories. We compare two architectures: an all-photonic entanglement generation switch (EGS) that repeatedly attempts Bell-state measurements (BSM) without storing qubits, and a quantum memory-equipped switch that buffers entanglement and triggers measurements only when heralded connectivity is available (herald-then-swap control). These two designs trade off simple, memoryless operation that avoids decoherence and memory-induced latency against heralding-based control that buffers entanglement to use BSMs more efficiently. We formalize both models under a common hardware abstraction and characterize their achievable rate-fidelity regions, yielding a benchmarking methodology that translates hardware and protocol parameters into network-level performance. Numerical evaluation quantifies the rate-fidelity tradeoffs of both models, identifies operating regions in which each architecture dominates, and shows how hardware and protocol knobs can be tuned to meet application-specific targets.

Rate-Fidelity Tradeoffs in All-Photonic and Memory-Equipped Quantum Switches

Abstract

Quantum entanglement switches are a key building block for early quantum networks, and a central design question is whether near-term devices should use only flying photons or also incorporate quantum memories. We compare two architectures: an all-photonic entanglement generation switch (EGS) that repeatedly attempts Bell-state measurements (BSM) without storing qubits, and a quantum memory-equipped switch that buffers entanglement and triggers measurements only when heralded connectivity is available (herald-then-swap control). These two designs trade off simple, memoryless operation that avoids decoherence and memory-induced latency against heralding-based control that buffers entanglement to use BSMs more efficiently. We formalize both models under a common hardware abstraction and characterize their achievable rate-fidelity regions, yielding a benchmarking methodology that translates hardware and protocol parameters into network-level performance. Numerical evaluation quantifies the rate-fidelity tradeoffs of both models, identifies operating regions in which each architecture dominates, and shows how hardware and protocol knobs can be tuned to meet application-specific targets.
Paper Structure (22 sections, 2 theorems, 28 equations, 6 figures)

This paper contains 22 sections, 2 theorems, 28 equations, 6 figures.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. System Description
  4. Fidelity and Quantum Noise Model
  5. Link-level Entanglement Generation Model
  6. Logical Model 1: All-Photonic Switch
  7. System Formulation
  8. Throughput Region
  9. End-to-End Entanglement Fidelity
  10. Logical Model 2: Quantum Switch with Internal Memories (Herald-Then-Swap Control)
  11. System Formulation
  12. Throughput Region
  13. End-to-End Entanglement Fidelity
  14. Numerical Results
  15. Block-based LLEG Protocol in Memory-Equipped Models
  16. ...and 7 more sections

Key Result

Theorem 1

For the EGS model with $B$ BSAs and per-node multiplexing degrees $\{S_i\}$, the maximum expected aggregate end-to-end success rate is and $S_{\max}\triangleq \max_{i} S_i.$

Figures (6)

  • Figure 1: Graphical illustration of (a) an EGS, (b) a memory-equipped switch, (c) the time-slot operation of an EGS, and, (d) the time slot operation of a memory-equipped switch. Both of the switches in illustrations (a) and (b) use $S_i = 2$ for every $i$, and $B = 2$. For the memory-equipped model in (b), $M_i = 2$ for every node $i$.
  • Figure 2: Maximum total throughput $\hat{R}_{\mathrm{mem}}^{\mathrm{sec}}$ as a function of block size $K$ and link length $L$; red dashed rectangles mark the optimal $K$ for each $L$.
  • Figure 3: End-to-end fidelity heatmap versus block size $K$ and $f_{\mathrm{pulse}}$.
  • Figure 4: Utilities versus block size $K$.
  • Figure 5: Baseline comparison of EGS and memory-equipped switching.
  • ...and 1 more figures

Theorems & Definitions (4)

  • Theorem 1: Closed form for maximum total throughput
  • Lemma 1
  • proof
  • proof