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Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction

Jiaping Tang, Jianan Mu, Tianyun Ma, Zhiteng Chao, Jing Ye, Huawei Li

TL;DR

This work proposes Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs, and introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles and strategic trace pruning to eliminate state pollution effects.

Abstract

Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs.

Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction

TL;DR

This work proposes Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs, and introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles and strategic trace pruning to eliminate state pollution effects.

Abstract

Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bug localization techniques have achieved remarkable success in software domains and shown promise for hardware description languages, their effectiveness severely degrades in sequential designs. Unlike software programs, hardware designs exhibit intrinsic temporal characteristics that create fundamental challenges: timing misalignment between bug activation and observation, and progressive error propagation through state elements that obscures the root cause. To address these limitations, we propose Pecker, a novel bug localization framework that reconstructs the broken causal chain in sequential designs. Our approach introduces two key innovations: temporal backtracking using Estimated Minimal Propagation Cycles to identify potential activation cycles, strategic trace pruning to eliminate state pollution effects. We evaluate Pecker on comprehensive benchmarks comprising both combinational and sequential circuits. Experimental results demonstrate that Pecker effectively localizes 51%/80%/85% bugs within Top-1/3/5 ranks respectively, significantly outperforming state-of-the-art techniques. Notably, Pecker maintains robust performance across circuit complexities while existing methods exhibit severe degradation on sequential designs.
Paper Structure (23 sections, 3 equations, 6 figures, 3 tables, 2 algorithms)

This paper contains 23 sections, 3 equations, 6 figures, 3 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Background
  3. Bug Localization in the Software Domain
  4. Related Works
  5. Motivation and Observation
  6. Pecker Framework
  7. Building the Program Dependency Graph for Hardware Designs
  8. Analyzing Estimated Minimal Propagation Cycles
  9. Localizing Potential Activation Cycles
  10. Pruning Execution Traces to Isolate Initial Fault Effect
  11. Calculating Dual Suspiciousness Scores
  12. Experiment
  13. Experimental Setup
  14. Implementation
  15. Evaluation Metrics
  16. ...and 8 more sections

Figures (6)

  • Figure 1: (a): Bug localization accuracy of Tarsel Wu_ICCD_2022 and Detaque Hu_TCAD_2025 on combinational and sequential circuits; (b): A HDL code snippet along with its execution trace and statues under specified inputs, where the buggy line (line 6) is highlighted in red, and the corresponding correct line is highlighted in green; (c): A program dependency graph corresponding to (b) and the bug activates at cycle 1, propagates to the registers, and is observed at cycle 2.
  • Figure 2: The overall workflow of SBFL.
  • Figure 3: Motivating Example.
  • Figure 4: The framework of Pecker.
  • Figure 5: Match and mismatch ratio between estimated and true activation cycles.
  • ...and 1 more figures