No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth

TL;DR

The ZX interleaving syndrome extraction is proposed, which preserves the full fault distance of $d$ for any surface-code layout with regular stabilizer tiles at minimum depth, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates.

Abstract

Hook errors are a major challenge in implementing logical operations with the surface code, because they can reduce the fault distance below the code distance. This motivates syndrome-extraction circuits that suppress hook-error effects for the stabilizer layouts that appear during logical operations. However, the existing methods either increase circuit depth or require simultaneous execution of measurements and CNOT gates, both of which introduce additional overheads and degrade the threshold. We propose the ZX interleaving syndrome extraction, which preserves the full fault distance $d$ for any surface-code layout with regular stabilizer tiles at minimum depth, i.e., four layers of CNOT gates, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates. The key idea is to interleave the Z and X stabilizer tiles so that hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm that the proposed method achieves a full fault distance of $d$, whereas the best existing minimum-depth approach achieves $d-1$. Since the full fault distance is achievable for any regular tiling layout of the surface code, the proposed method may serve as an indispensable technique for practical fault-tolerant quantum computation.

Figures (21)

• Figure 1: Rotated surface code with code distance $d=5$.
• Figure 2: Surface code layout of the logical Pauli-XX measurement using lattice surgery.
• Figure 3: Syndrome extraction circuit. The Z error is coupled to the two data qubits via the CNOT gates shown in blue.
• Figure 4: An order of the CNOT gates in the syndrome extraction circuit that preserves the fault distance in the memory layout.
• Figure 5: Decoding graph for the Z detectors in the surface code.