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Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow

Hang Gu, Teng Wang, Qianyu Cheng, Jinao Li, Zhendong Zheng, Lei Gong, Wenqi Lou, Xi Li, Xuehai Zhou

TL;DR

Hermes is presented, a unified high-performance NTT architecture based on hybrid dataflow that exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core.

Abstract

Fully Homomorphic Encryption (FHE) relies heavily on the Number Theoretic Transform (NTT), making NTT a major performance bottleneck due to its intensive polynomial computations. Hybrid Homomorphic Encryption (HHE), which integrates arithmetic and logic FHE, further requires support for multiple NTT lengths. However, existing accelerators mainly optimize NTT throughput and do not provide unified support for HHE. This paper presents Hermes, a unified high-performance NTT architecture based on hybrid dataflow. Hermes exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core. A conflict-free on-chip fragmentation algorithm is introduced to resolve bank conflicts and enable burst HBM access, while an efficient dataflow improves computational intensity through data reuse, reducing bandwidth demand. Experimental results show that Hermes supports multiple NTT lengths and achieves up to 13.6x and 1.3x higher throughput than state-of-the-art GPU and FPGA accelerators, respectively. Our source code is available at https://anonymous.4open.science/r/Hermes_conf-4E6F.

Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow

TL;DR

Hermes is presented, a unified high-performance NTT architecture based on hybrid dataflow that exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core.

Abstract

Fully Homomorphic Encryption (FHE) relies heavily on the Number Theoretic Transform (NTT), making NTT a major performance bottleneck due to its intensive polynomial computations. Hybrid Homomorphic Encryption (HHE), which integrates arithmetic and logic FHE, further requires support for multiple NTT lengths. However, existing accelerators mainly optimize NTT throughput and do not provide unified support for HHE. This paper presents Hermes, a unified high-performance NTT architecture based on hybrid dataflow. Hermes exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core. A conflict-free on-chip fragmentation algorithm is introduced to resolve bank conflicts and enable burst HBM access, while an efficient dataflow improves computational intensity through data reuse, reducing bandwidth demand. Experimental results show that Hermes supports multiple NTT lengths and achieves up to 13.6x and 1.3x higher throughput than state-of-the-art GPU and FPGA accelerators, respectively. Our source code is available at https://anonymous.4open.science/r/Hermes_conf-4E6F.
Paper Structure (16 sections, 10 figures, 3 tables, 1 algorithm)

This paper contains 16 sections, 10 figures, 3 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Motivation
  4. Roofline Model Analysis
  5. Design Opportunities
  6. Hermes Methodology
  7. Proposed Architecture
  8. Efficient Dataflow
  9. Conflict-Free On-Chip Fragmentation Algorithm
  10. Twiddle Factors Arrangement
  11. Experimental Results
  12. Experimental Setup
  13. Hardware Utilization
  14. Performance
  15. Relationship Between Bandwidth Utilization and Performance
  16. ...and 1 more sections

Figures (10)

  • Figure 1: (a) Stage-based and (b) pipeline-based NTT architectures. Taking $N = 16$ and $p = 4$ as an example, the figure depicts the computational behavior of the $p$ butterfly units in the first iteration.
  • Figure 2: Roofline model of the two architectures.
  • Figure 3: Hybrid dataflow-based NTT architecture. Here, we set $N_{part}=4, S_{part}=2, p=2$. The input and output orders are rearranged for illustration.
  • Figure 4: The overall architecture of Hermes including dependent and independent stages with $p/2$ NTT units per stage.
  • Figure 5: Internal computation units of NTT (NTTU, BU).
  • ...and 5 more figures