Applicability and Limitations of Quantum Circuit Cutting in Classical State-Vector Simulation

Abstract

Circuit cutting partitions a large quantum circuit into smaller subcircuits that can be executed independently and recombined by classical post-processing. In classical state-vector simulation with full-state reconstruction, the runtime is governed by a trade-off between reduced subcircuit size and the overheads of exponentially many subcircuits and full-state reconstruction. For equal partitioning, we derive threshold conditions on the number of cuts below which cutting reduces the wall-clock time. State-vector experiments validate the predicted speedup boundary up to 24 qubits, and a runtime breakdown up to 30 qubits identifies crossovers at $q \approx 18$ and $q \approx 22$ where merging overtakes first preprocessing and then subcircuit simulation. As a practical guideline, we show that under a 10-minute wall-clock budget, two-way cutting extends the maximum feasible qubit count by 4 to 6 qubits relative to simulation without cutting.

Figures (9)

• Figure 1: An original circuit which we can partition by one cut. For two or more cuts, the circuit is extended by appending additional copies of this circuit after removing the initial Hadamard gates.
• Figure 2: Measured relative speedup $\Delta = (T_\mathrm{cut} - T_{\mathrm{orig}})/T_{\mathrm{orig}}$ on the $(q,\,c_{\mathrm{total}})$ plane for (a) two-way ($n=2$, $q = 2,4,\ldots,24$, $c_{\mathrm{total}} = 1,\ldots,10$) and (b) three-way ($n=3$, $q = 3,6,\ldots,24$, $c_{\mathrm{total}} = 2,4,\ldots,14$) equal partitioning. Blue indicates speedup ($\Delta < 0$); red indicates slowdown ($\Delta > 0$). The dashed line shows the theoretical threshold derived in Sec. \ref{['sec:threshold']}. The solid line shows a linear boundary fitted to the measured data by a weighted SVM classifier. Both boundaries confirm that the speedup region grows linearly with $q$, though the measured boundary is steeper than the theoretical prediction, as discussed in Sec. \ref{['sec:Validation of threshold conditions']}.
• Figure 3: Runtime breakdown of two-way circuit cutting with $c_{\mathrm{total}}=6$ cuts, as a function of the number of qubits $q$. Three phases are shown: preprocessing ($T_\mathrm{pre}$), subcircuit simulation ($T_{\mathrm{sub}}$), and merging ($T_{\mathrm{merge}}$). Vertical dotted lines mark the two crossover points: around $q \approx 18$, where merging is no longer a minor overhead relative to preprocessing, and around $q \approx 22$, where merging overtakes subcircuit simulation.
• Figure 4: Speedup boundary on the $(q,\,c_{\mathrm{total}})$ plane for two-way partitioning ($n=2$) at four depth configurations ($p = 0, 2, 3, 4$, corresponding to $D \propto 1, 10^2, 10^3, 10^4$ additional gate layers). Each colored line shows the $\Delta = 0$ boundary obtained by a weighted SVM fit at the corresponding depth. Cutting is beneficial below each line. The dashed black line shows the theoretical threshold derived in Sec. \ref{['sec:threshold']}. The boundaries remain close to one another across all tested depths, confirming that the qubit-count-based threshold provides a reasonable first-order guideline even for circuits of varying depth.
• Figure 5: Maximum feasible qubit count within a 10-minute wall-clock budget, as a function of circuit depth $D$. The dashed blue line shows the original (uncut) simulation and the solid orange line shows two-way cutting with $c_{\mathrm{total}}=6$. The shaded region highlights the improvement from cutting. Annotated arrows indicate the qubit-count gain at each depth: 4 qubits for $p=0,2,3$ and 6 qubits for $p=4$, extending the feasible range from 22--26 (no cutting) to 28--30 (with cutting).