Closing the Loop: Resource-aware Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling

Abstract

Hybrid quantum-classical neural networks (HQNNs) integrate quantum circuits with classical layers, each operating under fundamentally different computational paradigms, which makes hardware resource estimation challenging. The training of quantum circuits on real devices requires thousands of circuit executions, which is impractical on current NISQ devices. Therefore, most HQNNs are evaluated on classical simulators, with hardware cost approximated using floating-point operations (FLOPs). However, FLOPs and existing quantum resource estimation methods (e.g., gate counts) overlook key quantum hardware-specific factors such as gate durations, limited qubit connectivity, and noise, all of which ultimately determine the true cost and scalability of quantum circuits. In this paper, we propose an analytical quantum cost model that estimates quantum hardware resources using real backend calibration data, incorporating gate durations, routing overheads, and noise-induced sampling inefficiencies. To complement this, we develop a classical cost model that converts FLOPs into device-specific throughput, enabling a unified time-based representation of hardware resource cost for both subsystems of HQNNs. Building on these analytical models, we present Hyb-HANAS, a hardware-aware hybrid neural architecture search framework, which jointly optimizes accuracy, hardware cost, and parameter count using NSGA-II. Hyb-HANAS identifies Pareto-optimal trade-offs and cross-domain co-adaptation between classical and quantum components of HQNNs. Beyond NAS, the proposed analytical quantum cost model is broadly applicable to quantum hardware benchmarking, compiler evaluation, and training-time estimation of quantum circuits on NISQ devices.

Figures (8)

• Figure 1: (Top) An abstract illustration of HQNN. (bottom) FLOPs, parameter count, and wall-clock time (averaged over 5 runs) comparison of quantum circuits for different depths and qubit counts on two different backend quantum simulators. Since the FLOPs are in the order of thousands compared to the parameters in the order of hundreds, the parameter count is scaled by 50 for better visualization.
• Figure 2: FLOPs vs. accuracy (left) and parameters vs. accuracy (right) plots for hybrid NAS with fixed classical components. Since quantum layers contribute no FLOPs, the FLOPs-accuracy plot collapses into a vertical line, producing an uninformative Pareto front. In contrast, parameter-based profiling captures quantum layer variations, yielding a more meaningful distribution of architectures and a relatively well-defined Pareto front.
• Figure 3: Original vs. Transpiled circuits. For a small $4$-qubit circuit, the single- and two-gate count, respectively, increased from $8$ to $24$ and $4$ to $7$, post transpilation. Transpilation penalizes circuits with more qubits by inserting more SWAP gates due to limited qubit connectivity in NISQ devices, i.e., more active qubits thus lead to higher routing complexity.
• Figure 4: Overview of the Hyb-HANAS framework. The workflow includes configuration setup, NSGA-II-based multi-objective evolutionary search, and hardware-aware feedback from the analytical quantum cost model. The process jointly optimizes accuracy, total cost, and parameters, producing Pareto-optimal HQNN architectures with hardware-aware cost estimation.
• Figure 5: Analytical model's estimated time vs. IBM Qiskit scheduler time one (a) ibm_torino and (b) FakeWashington.