A 200 dB Dynamic Range Radiation-Hard Delta-Sigma Current Digitizer for Beam Loss Monitoring

Abstract

This paper presents a radiation-hardened current-mode delta-sigma ADC fabricated in a standard 130~nm CMOS technology and qualified for total ionizing doses up to 100~Mrad. The converter is designed for beam loss monitoring applications in high-energy physics, where it must handle input currents spanning nine decades, from 1~mA down to 1~pA, while providing a fast 10~\textmu s response time for machine protection. To meet these conflicting requirements, the architecture exploits the inherent trade-off between resolution and acquisition time: a first-order modulator sampled at 20~MHz delivers 11-bit effective resolution within the critical 10~\textmu s window for the mA current range. Extended integration times of up to 100~s enable the sub-picoampere resolution required for beam alignment and background monitoring and provides an operational dynamic range exceeding 200~dB. The chip integrates two independent channels, consumes 25~mW from a 1.2~V supply, and includes radiation-hardening techniques such as triple-redundant digital logic and SEU-tolerant comparator banks. Post-irradiation measurements up to 100~Mrad show no performance degradation, and the uncalibrated integral nonlinearity remains within [+0.2\%, --0.3\%] of full scale over the 1~mA to 5~\textmu A range. The converter's flexibility and radiation tolerance make it suitable not only for the HL-LHC beam loss monitoring upgrade but also for other precision current measurement applications in harsh environments.

Figures (12)

• Figure 1: Block diagram of the first-order delta-sigma ADC. The modulator operates in current mode, with both the sensor input and the feedback compensation implemented as currents. The clocked comparator outputs a digital bitstream, which is subsequently processed and also fed back to control the compensation current.
• Figure 2: Calculated intrinsic dynamic range of a first-order delta-sigma modulator as a function of acquisition time, for static input signals. The dynamic range spans from a single high pulse ('1') to an all-ones bitstream. The plot assumes a constant sampling frequency of 20 MHz.
• Figure 3: The noise transfer function (NTF) illustrates how signals injected after the integrator, acting as a loop filter, are shaped when referred to the input. The complementary filter response provides substantial attenuation in the low-frequency band of interest, balanced by a contained amplification at higher frequencies.
• Figure 4: Simplified schematic of the implemented ADC. The fully differential integrator converts the single-ended sensor current into a differential signal. Adaptive clock control, complementary switching for the reference current, and reset switches ensuring DC loop continuity are highlighted. Integrating capacitors are sized to 60 pF.
• Figure 5: Simplified schematic of the operational transconductance amplifier (OTA). A two-stage, cascode-compensated topology with a PMOS folded cascode input stage and a class-AB rail-to-rail output stage biased through a translinear loop. Common-mode feedback (CMFB) regulation amplifier shown in the bottom left.