Analog Time Multiplexing for Digital-to-Analog Conversion

TL;DR

This preprint proposes that time multiplexing be performed in the analog domain and robustness against dynamic effects is achieved.

Abstract

The signal bandwidth of Digital to Analog Converters based on Sigma Delta Modulation is limited by speed constrains. Time-Interleaving allows coping with complexity vs. speed by replacing the original architecture by M parallel paths. These path are clocked at a frequency M times smaller and their digital outputs time multiplexed. This is then converted to analog by means of a Digital to Analog Converter clocked at the high rate. This preprint proposes that time multiplexing be performed in the analog domain. As a result robustness against dynamic effects is achieved.

Figures (7)

• Figure 1: EF-SDM architecture.
• Figure 2: Scheme for the TI SDM based DAC.
• Figure 3: a) Output stage of the SDM based DAC and b) the equivalent discrete-time model.
• Figure 4: PSD of $V(w)$ (Fig. 1) and $G(w)$ (Fig. 3.a) from 0 to $f_H /2$.
• Figure 5: Effect of jitter on the waveform at the output of the DAC.