Computing with many encoded logical qubits beyond break-even

TL;DR

Computations that outperform their unencoded counterparts in the high-rate QED/QEC codes are demonstrated and evidence that high-rate QED/QEC codes are viable on contemporary quantum computers for near-term beyond-classical-scale computation is provided.

Abstract

High-rate quantum error correcting (QEC) codes encode many logical qubits in a given number of physical qubits, making them promising candidates for quantum computation. Implementing high-rate codes at a scale that both frustrates classical computing and improves performance by encoding requires both high fidelity gates and long-range qubit connectivity -- both of which are offered by trapped-ion quantum computers. Here, we demonstrate computations that outperform their unencoded counterparts in the high-rate $[[ k+2,\, k,\, 2 ]]$ iceberg quantum error detecting (QED) and $[[ (k_2 + 2)(k_1 + 2),\, k_2k_1,\, 4 ]]$ two-level concatenated iceberg QEC codes, using the 98-qubit Quantinuum Helios trapped-ion quantum processor. Utilizing new gadgets for encoded operations, we realize this "beyond break-even" performance with reasonable postselection rates across a range of fault-tolerant (FT) and partially-fault-tolerant (pFT) component and application benchmarks with between $48$ and $94$ logical qubits. These benchmarks include FT state preparation and measurement, QEC cycle benchmarking, logical gate benchmarking, GHZ state preparation, and a pFT quantum simulation of the three-dimensional $XY$ model of quantum magnetism. Additionally, we illustrate that postselection rates can be suppressed by increasing the code distance via concatenation. Our results represent state-of-the-art logical component and state fidelities and provide evidence that high-rate QED/QEC codes are viable on contemporary quantum computers for near-term beyond-classical-scale computation.

Figures (32)

• Figure 1: Iceberg codes and their concatenation(a) Grid layout depicting stabilizers and logical operators of the $\mathcal{I}_{8}\circ\mathcal{I}_{6}$ code. (b) SPAM infidelity per logical qubit across experiments, some using leakage-heralded measurement and/or non-destructive extraction of $S_X$. Note that the $\mathcal{I}_{8}\circ\mathcal{I}_{6}$ SPAM experiment recorded no logical errors, bounding the infidelity as indicated in the rightmost column. (c) Acceptance rates across each SPAM experiment. When leakage-heralded measurement is used, the leakage acceptance rate is outlined (black, dashed). (d) The QEC cycle for the $\mathcal{I}_{8}\circ\mathcal{I}_{6}$ code; Z stabilizer syndrome extraction is shown, and is followed by extraction of the $X$ stabilizers. EDZ denotes $d=2$ Bell-pair syndrome extraction. (e) Fidelity and acceptance rate (AR) as a function of number of QEC/SE cycles for (concatenated) iceberg codes for different logical basis input states. All uncertainties reported through this work denote 68% Wilson confidence intervals unless otherwise noted, with point estimates corresponding to empirical observations. Acceptance and fidelity curves are obtained from fitting the data to exponential decays using maximum likelihood estimation. Fit values are given in Methods \ref{['sec:QEC Benchmark']}.
• Figure 2: Logical gate benchmarking and GHZ state preparation(a) Circuit gadgets for an inter-block $U_{ZZ}$ gate and the FANOUT gate. Here $t = q_0$ is the "top" qubit and $b = q_{n-1}$ is the "bottom" qubit on each code block with indices labeling the code block. (b) Infidelity per logical gate for each gate considered in the main text, reported alongside the physical $U_{ZZ}(\pi/2)$ fidelity from helios, both including ($\tilde{\epsilon}_{2Q}$) and excluding (2QRB) transport overheads. (c) Preparing a GHZ state distributed over many $\mathcal{I}_{4}$ code blocks using the log-depth FANOUT tree, represented in shorthand by controlled gates with stars, followed by extraction of the $\prod_i \overline{X}^i$ GHZ stabilizer where red (purple) gates couple to qubit $q_0$ ($q_5$) alone on each block. (d) GHZ state preparation in the $\mathcal{I}_{8}\circ\mathcal{I}_{6}$ code as described in the text. (e) GHZ infidelity and acceptances across the various experiments. Note that the $\mathcal{I}_{8}\circ\mathcal{I}_{6}$ ($k=48$) and leakage-heralded $15\times \mathcal{I}_{4}$ ($k=60$) experiments both recorded no errors.
• Figure 3: Mirror benchmarking of encoded Hamiltonian simulation(a) The natural edge-$6$-coloring of the $4\times 4\times 4$ periodic cubic lattice. Edges connecting the periodic boundaries are omitted for visual clarity, but the corresponding gates are included in the circuits executed. (b) Logical mirror benchmarking circuits used to assess the fidelity of Hamiltonian simulation. For the purposes of illustration, the circuit shown uses an $\mathcal{I}_{10}$ code with dynamics governed by a 6-regular graph on 10 vertices. (c) Logical gates implementing the first-order Trotter circuit depicted in (b). In the "reverse" half of the circuit, the inverse gates (dashed) are used in the opposite order. (d) Fidelity estimate and acceptance rate as a function of total Trotter steps in the full mirrored circuit. The fidelity estimate inset displays the last three points on a log scale for clarity. Each heuristic depolarizing error model (dashed) is labeled with its corresponding effective 2Q error rate $\tilde{\epsilon}_{2Q}$ (see Methods \ref{['sec:Helios']}, SI Sec. \ref{['sec:64lq_data']}).
• Figure S1: Two-branch state preparation gadget in the $\mathcal{I}_{k}$ codes.(a) Two-branch tree specifying preparation of the logical zero state of the $\mathcal{I}_{48}$ code. Nodes are labeled with the index $i$ corresponding to qubit $q_i$ in the code. Qubit $q_0$ is initialized in the $|+\rangle$ state while all other qubits are initialized in the $|0\rangle$ state; directed arrows indicate the control and target of CX gates between the qubits and all arrows terminating on nodes at the same vertical height are performed in parallel. The red bracket connecting the terminal nodes indicates that the corresponding operator $Z_{48}Z_{49}$ will be read out by coupling to an ancilla. (b) The circuit gadget instantiating the two-branch tree in the $\mathcal{I}_{10}$ code for illustration.
• Figure S2: Log-depth state preparation gadget for $\mathcal{I}_{k}$ codes.(a) The balanced tree structure specifying preparation of the logical zero state in the $\mathcal{I}_{48}$ code. As before, red brackets indicate pairs of qubits whose $ZZ$ operator will be read out by coupling to an ancilla (note that in this particular case, the qubit with index $m$ on the left connects to the qubit with index $m-1$ on the right). (b) Circuit instantiation of the log-depth tree in the $\mathcal{I}_{10}$ code, as also depicted in Fig. \ref{['fig:computing']}. Pauli $X$ gates in the circuit implement the DFS-based error mitigation discussed below; note that this flips the noiseless value of the ancilla measurements that is checked as part of the repeat-until-success protocol.

Theorems & Definitions (10)

• Definition 1
• Definition 2
• Proposition 1
• proof
• Definition 3
• Proposition 2
• proof
• Definition 4
• Proposition 3
• proof