Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler

Xinxin Wang, Lixian Yan, Shuhan Liu, Luke Upton, Zhuoqi Cai, Yiming Tan, Shengman Li, Koustav Jana, Peijing Li, Jesse Cirimelli-Low, Thierry Tambe, Matthew Guthaus, H. -S. Philip Wong

TL;DR

An OpenGCRAM compiler supporting both SRAM and GCRAM is created, which enables systematic identification of optimal heterogeneous memory configurations for AI tasks under specified performance metrics.

Abstract

As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain Cell RAM (GCRAM) offers higher density, lower power, and tunable retention, expanding the design space beyond conventional SRAM. To this end, we create an OpenGCRAM compiler supporting both SRAM and GCRAM. It generates macro-level designs and layouts for commercial CMOS processes and characterizes area, delay, and power across user-defined configurations. The tool enables systematic identification of optimal heterogeneous memory configurations for AI tasks under specified performance metrics.

Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler

TL;DR

An OpenGCRAM compiler supporting both SRAM and GCRAM is created, which enables systematic identification of optimal heterogeneous memory configurations for AI tasks under specified performance metrics.

Abstract

As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain Cell RAM (GCRAM) offers higher density, lower power, and tunable retention, expanding the design space beyond conventional SRAM. To this end, we create an OpenGCRAM compiler supporting both SRAM and GCRAM. It generates macro-level designs and layouts for commercial CMOS processes and characterizes area, delay, and power across user-defined configurations. The tool enables systematic identification of optimal heterogeneous memory configurations for AI tasks under specified performance metrics.
Paper Structure (15 sections, 11 figures, 2 tables)

This paper contains 15 sections, 11 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Heterogeneous Memory Architectures
  4. EDA Tools for SRAM and GCRAM
  5. Design Options for Heterogeneous On-Chip Memory Architectures
  6. OpenGCRAM Compiler
  7. Compiler Implementation
  8. GCRAM Macro Architecture
  9. Design Explorations with OpenGCRAM
  10. Area Comparison
  11. Frequency, Bandwidth, and Power Comparison
  12. GCRAM Retention Modulation
  13. Heterogeneous Memory Design Space Exploration
  14. Future Work
  15. Conclusion

Figures (11)

  • Figure 1: Schematics of (a) 2T Si-Si GCRAM, (b) 2T OS-Si GCRAM, and (c) 6T SRAM bitcells. The green-colored transistor is an ultra-low-leakage OS FET.
  • Figure 2: Comparison of SRAM and GCRAM variants across density, speed, retention, and power efficiency.
  • Figure 3: Methodology of (a) porting the compiler to new technology nodes and (b) adding support for new memory technologies.
  • Figure 4: GCRAM macro architecture adopted by OpenGCRAM.
  • Figure 5: Generated layout of a 32× 32 GCRAM macro with bitcell array, dual-port peripherals, and power rings.
  • ...and 6 more figures