LUTstructions: Self-loading FPGA-based Reconfigurable Instructions

TL;DR

The concept of having reconfigurable instructions by incorporating reconfigurable areas in a softcore is explored, which follows a relatively-recently proposed computer architecture concept for seamlessly loading instruction implementation-carrying bitstreams from main memory.

Abstract

General-purpose processors feature a limited number of instructions based on an instruction set. They can be numerous, such as with vector extensions that include hundreds or thousands of instructions, but this comes at a cost; they are often unable to express arbitrary tasks efficiently. This paper explores the concept of having reconfigurable instructions by incorporating reconfigurable areas in a softcore. It follows a relatively-recently proposed computer architecture concept for seamlessly loading instruction implementation-carrying bitstreams from main memory. The resulting softcore is entirely evaluated on an FPGA, essentially having an FPGA-on-an-FPGA for the instruction implementations, with no notable operating frequency overhead. This is achieved with a custom FPGA architecture called LUTstruction, which is tailored towards low-latency for custom instructions and wide reconfiguration, as well as a soft implementation for the purposes of architectural exploration.

Figures (10)

• Figure 1: FPGA-extended computer architecture arc22fpgaext.
• Figure 2: FPGA architecture for reconfigurable instructions.
• Figure 3: Placing compulsory registers on every S LUTs, S=2.
• Figure 4: Parallel configuration of same-sized fabric chunks.
• Figure 5: Adopting the R-type instruction format.