TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence

TL;DR

TOM exploits the synergy between ternary quantization and ROM to achieve extreme memory density and bandwidth, while preserving flexibility through a hybrid ROM-SRAM architecture designed for QLoRA-based tunability.

Abstract

The deployment of Large Language Models (LLMs) for real-time intelligence on edge devices is rapidly growing. However, conventional hardware architectures face a fundamental memory wall challenge, where limited on-device memory capacity and bandwidth severely constrain the size of deployable models and their inference speed, while also limiting on-device adaptation. To address this challenge, we propose TOM, a hybrid ROM-SRAM accelerator co-designed with ternary quantization, which balances extreme density with on-device tunability. TOM exploits the synergy between ternary quantization and ROM to achieve extreme memory density and bandwidth, while preserving flexibility through a hybrid ROM-SRAM architecture designed for QLoRA-based tunability. Specifically, we introduce: (1) a sparsity-aware ROM architecture that synthesizes ternary weights as standard-cell logic, eliminating area overhead from zero-valued bits; (2) a distributed processing architecture that co-locates high-density ROM banks with flexible SRAM-based QLoRA adapters and compute units; and (3) a workload-aware dynamic power gating scheme that exploits the logic-based nature of ROM to power down inactive banks, minimizing dynamic energy consumption. TOM achieves an inference throughput of 3,306 TPS using BitNet-2B model, demonstrating its effectiveness in delivering real-time, energy-efficient edge intelligence.

Figures (15)

• Figure 1: The architecture of a decoder-based Transformer.
• Figure 2: The ARC-e accuracy of LLaMA3-8B with different weight bit-widths liu2025paretoq. The ternary one (1.58-bit) achieves the pareto front considering both accuracy and memory consumption.
• Figure 3: The capacity and bandwidth of different memory. These memory cannot meet either capacity or bandwidth requirements of LLMs on edge.
• Figure 4: Zero-value bit percentage across ternary model layers. Ternary memory naturally shows high percentage of zero-valued weights. In order to further improve the zero-value bits percentage, we use '10' instead of '11' to encode -1. (a-d) show that the overall sparsity-ratio can be up to 94%, while INT2 or INT4 quantization typically is around 50% (e-f).
• Figure 5: Architecture of TOM. (a) TOM comprise multiple parallel Processing Lanes, each with multiple chained Matrix Vector Units and a shared Vector Unit. (b) Each MVU has its dedicated ROM for weight storage and SRAM for KV cache. The GEMV supports Ternary x FP8 for FFN and FP8 x FP8 for Attention, while sharing the adder tree. (c) Shared Vector Unit in each lane with special arithmetic function.