Demonstration of High-Performance Ultra-Wide Bandgap SrSnO$_3$ Top-Gated MOSFETs

Abstract

We report the demonstration of high-performance top-gated metal-oxide-semiconductor field-effect transistors (MOSFETs) based on the ultra-wide bandgap perovskite oxide SrSnO$_3$ (SSO). Using hybrid molecular beam epitaxy-grown SSO channels and ALD-deposited HfO$_2$ gate dielectrics, the devices exhibit field-effect mobility exceeding 65 cm$^2$/V$\cdot$s, an on-state current up to 194 mA/mm, an on/off current ratio above $10^8$, and a contact resistance of 0.66 $Ω\cdot$mm. The devices also show a near-ideal subthreshold slope of 68 mV/dec and negligible hysteresis, indicating a high-quality dielectric/semiconductor interface. These results establish SrSnO$_3$ as a promising ultra-wide bandgap oxide semiconductor platform for high-performance power electronic applications.

Figures (5)

• Figure 1: (a) The schematic of the radical-based hybrid MBE (hMBE) configuration for SrSnO$_3$ growth. (b) The High-resolution XRD 2$\theta$–$\omega$ scan of the sample. The inset shows the RHEED pattern of a pseudo-cubic phase La:SrSnO$_3$ film grown on pseudo-cubic phase GdScO$_3$ (110), acquired with the GdScO$_3$$[1\bar{1}0]_{\mathrm{orth}}$ direction.
• Figure 2: (a) An optical image of a $5\times5$ mm 15-nm-thick SSO/GSO (110) wafer with a millimeter ruler, illustrating the wafer size and optical transparency. (b-d) Room-temperature sheet resistance $R_{\mathrm{sheet}}$, sheet carrier density $n_{2\mathrm{D}}$, and Hall mobility $\mu_{\mathrm{Hall}}$ heatmaps from the $4\times4$ Hall bar array. One device in the upper left corner could not be measured due to damage during fabrication.
• Figure 3: (a) Cross-sectional schematic of a SSO MOSFET. (b) Transfer curves of eighteen devices with different $W_{\mathrm{ch}}$, $L_\mathrm{DS}$, and $L_\mathrm{G}$. (c – d) Data from a representative device with $W_{\mathrm{ch}} = 10\,\mu$m, $L_\mathrm{DS} = 5\,\mu$m, and $L_\mathrm{G} = 4\,\mu$m: (c) Semi-log $I_\mathrm{DS}$ – $V_\mathrm{GS}$ characteristics with $I_\mathrm{G}$ plotted in lighter color, (d) Linear $I_\mathrm{DS}$ – $V_\mathrm{GS}$ (black, left axis) and transconductance $g_\mathrm{m}$ (green, right axis) curves. The inset shows the enlarged curves with $V_\mathrm{DS}\,=\,0.1$ V.
• Figure 4: (a) $I_\mathrm{DS}$ – $V_\mathrm{DS}$ curves for $V_\mathrm{GS}$ from $-1$ to $4.5$ V in $0.5$ V increments. (b) The TLM plot for Cr/Au source/drain contacts: width-normalized total resistance $R_{\mathrm{tot}}W$ versus contact spacing $L$ with vertical (measurement) and horizontal (S/D-spacing) error bars. Linear fitting gives a sheet resistance of $R_{\mathrm{sh}}\approx 488.5\,\Omega/\square$ and an intercept of $2R_{\mathrm{c}}\approx 1.32\,\Omega\!\cdot\!\mathrm{mm}$, corresponding to $R_{\mathrm{c}}\approx 0.66\,\Omega\!\cdot\!\mathrm{mm}$.
• Figure 5: (a) Breakdown voltage comparison between SSO, IGZO, and Sn-doped Ga$_2$O$_3$ measured from the same two-terminal device geometry. A breakdown voltage of 800 V is observed in the SSO device. (b) COMSOL-simulated electric field distribution under 800 V bias, corresponding to a breakdown electric field of 6.4 MV/cm.