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CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection

Amisha Srivastava, Muskan Porwal, Kanad Basu

TL;DR

CryptRISC is the first RISC-V-based processor that combines cryptographic acceleration with hardware-level power side-channel resistance through an ISA-driven operand masking framework, providing optimized protection across algorithms including AES, SHA-256, SHA-256, SHA-512, SM3, and SM4.

Abstract

Cryptographic computations are fundamental to modern computing, ensuring data confidentiality and integrity. However, these operations are highly vulnerable to power side-channel attacks that exploit variations in power consumption to leak sensitive information. Masking is a widely used countermeasure, yet software-based techniques often introduce significant performance overhead and implementation complexity, while fixed-function hardware masking lacks flexibility across diverse cryptographic algorithms. In this paper, we present CryptRISC, the first RISC-V-based processor that combines cryptographic acceleration with hardware-level power side-channel resistance through an ISA-driven operand masking framework. Our design extends the CVA6 core with 64-bit RISC-V Scalar Cryptography Extensions and introduces two microarchitectural components: a Field Detection Layer, which identifies the dominant algebraic field of each cryptographic instruction, and a Masking Control Unit, which applies field-aware operand randomization at runtime. This enables dynamic selection of Boolean, affine, or arithmetic masking schemes based on instruction semantics, providing optimized protection across algorithms including AES, SHA-256, SHA-512, SM3, and SM4. Unlike prior approaches relying on static masking logic or software instrumentation, our method performs operand masking transparently within the execution pipeline without modifying instruction encoding. Experimental results show speedups up to 6.80$\times$ over baseline software implementations, with only a 1.86% hardware overhead relative to the baseline CVA6 core, confirming the efficiency and practicality of CryptRISC.

CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection

TL;DR

CryptRISC is the first RISC-V-based processor that combines cryptographic acceleration with hardware-level power side-channel resistance through an ISA-driven operand masking framework, providing optimized protection across algorithms including AES, SHA-256, SHA-256, SHA-512, SM3, and SM4.

Abstract

Cryptographic computations are fundamental to modern computing, ensuring data confidentiality and integrity. However, these operations are highly vulnerable to power side-channel attacks that exploit variations in power consumption to leak sensitive information. Masking is a widely used countermeasure, yet software-based techniques often introduce significant performance overhead and implementation complexity, while fixed-function hardware masking lacks flexibility across diverse cryptographic algorithms. In this paper, we present CryptRISC, the first RISC-V-based processor that combines cryptographic acceleration with hardware-level power side-channel resistance through an ISA-driven operand masking framework. Our design extends the CVA6 core with 64-bit RISC-V Scalar Cryptography Extensions and introduces two microarchitectural components: a Field Detection Layer, which identifies the dominant algebraic field of each cryptographic instruction, and a Masking Control Unit, which applies field-aware operand randomization at runtime. This enables dynamic selection of Boolean, affine, or arithmetic masking schemes based on instruction semantics, providing optimized protection across algorithms including AES, SHA-256, SHA-512, SM3, and SM4. Unlike prior approaches relying on static masking logic or software instrumentation, our method performs operand masking transparently within the execution pipeline without modifying instruction encoding. Experimental results show speedups up to 6.80 over baseline software implementations, with only a 1.86% hardware overhead relative to the baseline CVA6 core, confirming the efficiency and practicality of CryptRISC.
Paper Structure (32 sections, 2 equations, 6 figures, 10 tables)

This paper contains 32 sections, 2 equations, 6 figures, 10 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Overview of Algebraic Fields
  4. Power Side-Channel Attacks
  5. RISC-V Scalar Cryptography Extensions
  6. Related Works
  7. CryptRISC: Enhancing Cryptographic Acceleration in the CVA6 Core
  8. Integration of 64-bit RISC-V Scalar Crypto Instructions into CVA6 for CryptRISC
  9. Field-Aware Dynamic Masking in CryptRISC
  10. Dominant Algebraic Fields in Cryptographic Algorithms
  11. Field Detection Layer
  12. FDL Architecture.
  13. Extensibility
  14. Microarchitectural Masking Configuration
  15. Masking Control Unit
  16. ...and 17 more sections

Figures (6)

  • Figure 1: Power Side-Channel Attack flow on a RISC-V Processor: Attacker can exploit the power consumption variations during cryptographic operations to reveal sensitive data by analyzing power leakage at different stages of instruction execution of the processor.
  • Figure 2: Overview of pipeline flow in the proposed side-channel hardened processor, CryptRISC, with architectural blocks introduced in this work highlighted in red.
  • Figure 3: Translation of the symbolic field tag into masking metadata fields during decode.
  • Figure 4: Timing diagram showing MCU integration within the CryptRISC pipeline. Operand masking overlaps with operand fetch and does not delay CFU execution.
  • Figure 5: t-Test results for 64-bit AES, SM4, and SM3 operations in Cryptrisc . All instructions demonstrate masked behavior with limited leakage.
  • ...and 1 more figures