CQM: Cyclic Qubit Mappings

TL;DR

Cyclic qubit mappings (CQM), a dynamic remapping technique implemented during compilation to mitigate hardware heterogeneity by expanding and contracting logical qubits.

Abstract

Quantum computers show promise to solve select problems otherwise intractable on classical computers. However, noisy intermediate-scale quantum (NISQ) era devices are currently prone to various sources of error. Quantum error correction (QEC) shows promise as a path towards fault tolerant quantum computing. Surface codes, in particular, have become ubiquitous throughout literature for their efficacy as a quantum error correcting code, and can execute quantum circuits via lattice surgery operations. Lattice surgery also allows for logical qubits to maneuver around the architecture, if there is space for it. Hardware used for near-term demonstrations have both spatially and temporally varying error results in logical qubits. By maneuvering logical qubits around the topology, an average logical error rate (LER) can be enforced. We propose cyclic qubit mappings (CQM), a dynamic remapping technique implemented during compilation to mitigate hardware heterogeneity by expanding and contracting logical qubits. In addition to LER averaging, CQM shows initial promise given it's minimal execution time overhead and effective resource utilization.

Figures (6)

• Figure 1: Current quantum hardware systems have qubits with non-uniform error rates which lead to logical tiles with variable logical error rates $p_L$ (top left). Because of the long-running nature of error corrected programs (hours to days), the logical error rate of a given tile is likely unknown. Compilers which use static mappings (top) can result in placing qubits in more or less favorable positions, even though the errors may not be known but cannot provide a guarantee. The alternative (bottom) and our proposal is to have continuously changing mappings so that no program qubit is mapped to the same position for too long and instead we can guarantee the average case logical error rate for every tile.
• Figure 2: For this work we abstract away the physical requirements of all tiles (top left) so that every Surface Code tile is represented as a single colored square with 2 types of boundaries: Z (dashed) and X (solid). Tiles can be moved (top middle) by expending the patch into available ancillary space and then measuring old space. This can be done in a single code cycle. The boundaries can also be modified by shifting corners using adjacent ancillary space and expansion. This can be done in 3 cycles. We also utilize a lattice surgery version of CNOT gates for multi-qubit gates (bottom). To do so we measure ZZ between the control and a prepared intermediate (INT) ancilla and then measure XX between INT and the target. This can be done in 2 cycles.
• Figure 3: Constraints on how operations can be parallelized. In the top half the objective is to in parallel execute a CNOT between A and B and C and D. If the routing path in blue is already allocated for the CNOT between C and D then we must stall before executing the CNOT between A and B. This can also be true even if there is a path between A and B (top right) but not between the proper edge types. In the bottom, we sometimes are forced to perform rotations of the qubits rather than stalling for availability when qubits are packed densely.
• Figure 4: Left: ECR (Error per Clifford Rate) tracked on the IBM Kyoto machine for 30 days. Right: Logical error rate (LER) computed with Google's Stim simulator Gidney_2021 using physical error rates sampled from the IBM Kyoto machine over 30 days.
• Figure 5: In this proof of concept with a $2\times 1$ sized patch and a single logical qubit we have three options. The first is to keep A in either position 1 or in position 2 and when error rates are unknown mid computation, so too is the logical error rate (top). In our proposal, we simply modify the mapping of A throughout the program so that it spends equal time in every position and so gets the average case logical error rate guaranteed (bottom).