HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale

TL;DR

An overview of the hard- and software stack is provided, the underlying design principles are explained, some of the system's capabilities are demonstrated, and the system is made easily available over a web portal for use by the wider community.

Abstract

In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster than real time. This system, assembled at the UC San Diego Supercomputer Center, comprises a co-designed hard- and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. The architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with minimal constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following, we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system's capabilities and solicit feedback from the broader neuromorphic community. Examples are shown demonstrating HiAER-Spike's capabilities for event-driven vision on benchmark CIFAR-10, DVS event-based gesture, MNIST, and Pong tasks.

Figures (10)

• Figure 1: High-level system architecture of HiAER-Spike. (a) Neurons and synapses form the 'grey matter' of dense local interconnects in the system while long-range connections (between cores and FPGAs) form the 'white matter' of sparse global interconnects. (b) The hardware equivalent of (a) as implemented in our multi-core architecture on the FPGA. The grey matter inside each core is implemented as sequentially updated integrate-and-fire neurons, whose internal state is stored in neural membrane registers in URAM, whereas spike events are routed through synaptic look-up tables in HBM. The white matter is implemented as a hierarchical multicast bus (HiAER) interconnecting axon spike register modules that are stored in BRAM across cores.
• Figure 2: (a) Host programming interface with SNN compiler and low-level hardware interface. (b) Heterogeneous memory organization within a single core, as well as the off-chip HBM storing the synaptic connectivity table. On-chip URAM and BRAM store state variables of axons and neurons. The top-left panel shows the layout of the data structure in HBM, supporting parallelism of 16 neurons per single core.
• Figure 3: DVS Gesture example. Representation of a waving gesture frame processed into two 63×63 pixel channels corresponding to ON and OFF events, with overlapped visualization showing ON events (green), OFF events (red), and overlapping ON and OFF events (yellow). One of ten frames accumulated across a gesture.
• Figure 4: A 160x210-pixel Atari Pong frame (left) and the DVS representation of that frame (right) processed into two 84×84-pixel channels corresponding to ON and OFF events, with overlapped visualization showing ON events (green) and OFF events (red), detecting 27 OFF and 28 ON events in the current frame. The location of green ON pixels relative to red OFF pixels indicates the direction of motion (e.g. the ball in the center is moving diagonally towards the lower right).
• Figure 5: Test accuracy of the DVS gesture network compared across different model sizes and full-precision software models, quantized software models, and hardware.