PRISM: Photonics-Informed Inverse Lithography for Manufacturable Inverse-Designed Photonic Integrated Circuits

Abstract

Recent advances in photonic inverse design have demonstrated the ability to automatically synthesize compact, high-performance photonic components that surpass conventional, hand-designed structures, offering a promising path toward scalable and functionality-rich photonic hardware. However, the practical deployment of inverse-designed PICs is bottlenecked by manufacturability: their irregular, subwavelength geometries are highly sensitive to fabrication variations, leading to large performance degradation, low yield, and a persistent gap between simulated optimality and fabricated performance. Unlike electronics, photonics lacks a systematic, flexible mask optimization flow. Fabrication deviations in photonic components cause large optical response drift and compounding error in cascaded circuits, while calibrating fabrication models remains costly and expertise-heavy, often requiring repeated fabrication cycles that are inaccessible to most designers. To bridge this gap, we introduce PRISM, a photonics-informed inverse lithography workflow that makes photonic mask optimization data-efficient, reliable, and optics-informed. PRISM (i) synthesizes compact, informative calibration patterns to minimize required fabrication data, (ii) trains a physics-grounded differentiable fabrication model, enabling gradient-based optimization, and (iii) performs photonics-informed inverse mask optimization that prioritizes performance-critical features beyond geometry matching. Across multiple inverse-designed components with both electron-beam lithography and deep ultra-violet photolithography processes, PRISM significantly boosts post-fabrication performance and yield while reducing calibration area and turnaround time, enabling and democratizing manufacturable and high-yield inverse-designed photonic hardware at scale.

Figures (13)

• Figure 1: Comprehensive motivation. (a) Fabrication error causes severe performance and yield degradation on inverse-designed photonic components. (b) DUV fabrication is particularly challenging for inverse-designed photonic devices, often causing substantially larger performance degradation and lower yield than EBL. (c)Sensitivity map of device transmission under coupled process variations. The heatmap shows the transmission as a function of defocus coefficient and resist threshold, highlighting their joint impact on the post-fabrication response.
• Figure 2: Comprehensive motivation. (a) Standard mask correction is insufficient, as close geometry does not always lead to close optical response. (b) Low pixel-wise $\ell_2$ error does not necessarily imply good photonic performance. An unbalanced error distribution dominated by systematic over-/under-etch introduces a global bias in geometry and can degrade the FoM significantly, despite a comparable $L_2$ value. (c) Neural network fabrication model trained on calibration data might have poor generalization to unseen patterns and mislead ILT optimization.
• Figure 3: Illustration of a typical pattern transfer flow in chip fabrication. Patterns are first defined by either photolithography or E-beam lithography to form a resist image on an oxide-coated silicon wafer, followed by (2) resist development, (3) etching and resist removal to transfer the pattern into the underlying film, (4) material deposition (e.g., Cu fill), and (5) chemical-mechanical polishing to planarize the surface.
• Figure 4: Overview of proposed PRISM flow to accelerate photonic inverse design convergence.
• Figure 5: (a) Illustration of regular, random, and photonic device patterns for fabrication model learning. (b) Design images and post-fab wafer images form data/label pairs for fabrication model training.