A scalable non-superconducting tunnel junction technology

Abstract

Tunnel junctions are one of the key elements of chip-scale microsystems serving various technologies from classical microelectronics to quantum information. Aluminium and its oxide (AlOx) have dominated cryogenic tunnel junction technology for decades due to the high quality of AlOx barriers and Al superconducting properties below 1.2 K. However, many applications require non-superconducting junctions, either standalone or in combination with superconducting technology, motivating efforts to suppress Al superconductivity through magnetic fields, doping, or proximity effects -- approaches that so far suffered from integration compatibility and scalability issues. Here, we present a CMOS-compatible normal-metal tunnel junction technology based on TiW alloy and AlOx barriers. We demonstrate wafer-scale fabrication of TiW/Al-AlOx/TiW junctions and validate their performance in Coulomb blockade thermometers operating down to 20 mK, confirming robust normal-state behavior. This TiW-based architecture offers a scalable solution for non-superconducting tunnel junctions across a broad temperature range, enabling integration into advanced cryogenic, quantum and nanoelectronic chip-level systems.

Figures (6)

• Figure 1: a, A cross-sectional illustration of the fabrication process. b, A tilted SEM image showing a cross-type 2.1 $\mu$m junction after patterning the upper metal layer. c, Room-temperature probing data as a function of a realized junction width $L=d_\mathrm{J}-\mathrm{LWR}$ (see main text) over three wafers with different tunnel resistance levels as characterized by specific resistivity $\rho_\mathrm{t}$ (Methods). Markers denote the measurement data, and lines are fits to the data as specified in the main text. d, An SEM image of the CBT. Large islands between the junctions were included in the designs, leaving space for possible metal electroplating in future fabrication processes. The purple colour indicates an island and the red outline marks the junction. The different shades of gray represent the wiring layer and the base electrode of the trilayer gro, which alternate within the array.
• Figure 2: a, Normalised conductance $g/g_{\mathrm{T}}$ of the CBT as a function of bias voltage $V_{\mathrm{b}}$ at different temperatures. Inset: measurement scheme of the CBT. b, Comparison of the sample holder phonon temperature $T_{\rm p}$ to the electron temperature $T_{\rm CBT}$ measured by the secondary thermometry mode. Inset: differential conductance dip $\delta g$ versus $T_{\rm p}$. The dashed curve is the third-order polynomial fit, with fit domain indicated as shaded background, delivering $E_{\rm c}$ with fit error $<0.5\%$. Lower panel: the relative deviation $\Delta T=T_{\rm CBT}-T_{\rm p}$ normalised by $T_{\rm p}$, remaining mostly below $1\%$ (see main text). The small glitch at $T_{\rm p}\sim55~\rm mK$ is an artefact due to a change in the point-spacing of the $T_{\rm p}$ calibration.
• Figure 3: a, CBT electron temperature $T_{\rm CBT}$ with respect to $T_{\rm p}$ measured at different parallel magnetic fields. Each temperature step was held for $\sim2$ hours to ensure proper thermalization. The lower panel displays the relative deviation between field and zero-field measurement. The difference is defined as $\Delta T_{\rm B}= T_{0} - T(B_{||})$, where $T_{0}$ is the temperature extracted at zero field, serving as the normalisation reference. $T_{\rm CBT}$ was determined using MCMC simulations parametrised by prior zero-field measurements. b, Normalised differential conductance $g/g_{\mathrm{T}}$ of the CBT as a function of bias voltage $V_{\mathrm{b}}$ at different parallel fields and a fixed temperature $T_{\rm p} = 41$ mK. An additional panel shows the discrepancy introduced by the magnetic field, where the relative error is defined by normalising the field traces against the zero-field reference measurement.
• Figure 4: Electron temperature of the CBT ($T_{\rm CBT}$) from different devices as a function of phonon temperature $T_{\rm p}$. Each sample is measured one-by-one in separate cooldown instances.
• Figure 5: MCMC simulations of temperature dependence of the zero-bias differential conductance for different offset charge configurations. The yellow and blue lines represent maximal and minimal Coulomb suppression, respectively. The wide shaded area is the range of simulation outcomes with random offset charge for a CBT with one row of junctions. The smaller shadow region is the uncertainty for a CBT with 20 parallel rows. The solid green line denotes the mean of the former region and is used to extract $T_{\rm CBT}$ from the measured differential conductance.