Bidirectional Quantum Processor Interfacing by a 4-Kelvin Analog Signal Chain for Superconducting Qubit Control and Quantum State Readout

TL;DR

This work tackles the critical bottleneck of wiring and latency in interfacing room-temperature control electronics with superconducting qubits by proposing a complete 4 K cryogenic analog signal chain with bidirectional control and readout. The methodology centers on a PLL-based local oscillator, I/Q generation, 8-PSK demodulation, a 14 dB cryogenic LNA, and a set of cryogenic-ready blocks (DAC, VCO, I/Q modulator, and a 3-bit flash ADC), all validated through LTSpice simulations using 4 K CMOS models. Key contributions include achieving an I/Q phase error below $2^{\circ}$ and image rejection above $35$ dB, symbol error rate below $10^{-6}$ for 8-PSK, and end-to-end signal integrity with a simulated power dissipation of $199.7$ mW at 180 nm (scaling to ~88 mW at 65 nm). The results offer a modular, simulation-validated pathway toward scalable cryogenic quantum-control systems capable of reducing cabling, lowering thermal budgets, and enabling tighter integration with quantum error correction.

Abstract

This paper presents a comprehensive cryogenic analog signal processing architecture designed for superconducting qubit control and quantum state readout operating at 4 Kelvin. The proposed system implements a complete bidirectional signal path bridging room-temperature digital controllers with quantum processors at millikelvin stages. The control path incorporates a Phase-Locked Loop (PLL) for stable local oscillator generation, In-phase/Quadrature (I/Q) modulation for precise qubit gate operations, and a cryogenic power amplifier for signal conditioning. The readout path features a Low Noise Amplifier (LNA) with 14 dB gain and 8-Phase Shift Keying (8-PSK) demodulation for quantum state discrimination. All circuit blocks are designed and validated through SPICE simulations employing cryogenic MOSFET models at 180nm that account for carrier freeze-out, threshold voltage elevation, and enhanced mobility at 4 K. Simulation results demonstrate successful end-to-end signal integrity with I/Q phase error below 2°, image rejection ratio exceeding 35~dB, and symbol error rate below $10^{-6}$. This work provides a modular, simulation-validated framework for scalable cryogenic quantum control systems.

Figures (11)

• Figure 1: System architecture showing control and readout signal paths across temperature stages from 300 K to 20 mK.
• Figure 2: PLL architecture with XOR phase detector and RC loop filter.
• Figure 3: I/Q modulator with analog multipliers and power amplifier.
• Figure 4: Binary-weighted DAC with operational amplifier output.
• Figure 5: LNA using LT1028 with 14 dB gain for cryogenic readout.