A Magnon-Based Electric Field Controlled Magnetoelectric Device for Energy-Efficient Logic-in-Memory

TL;DR

This work introduces a magnetoelectric magnon memory (MEMM) device that enables non-volatile, low-power operation by electrically controlling magnetization and using magnon transport in a insulating antiferromagnet. A SrIrO$_3$/La-BiFeO$_3$/SrIrO$_3$ trilayer provides sub-100 ps switching and a ~1 mV readout contrast, which are connected to a compact spin-circuit model to predict >$100$ mV outputs and attojoule switching energies under optimized parameters. The authors design MEMM-based memory and logic blocks, including a 1T1R array, complementary and single-cell logic, a three-input majority gate, and demonstrate deep pipelining for a 32-bit ALU, highlighting the potential for dense, energy-efficient in-memory computing. Overall, MEMM shows promise as a scalable, high-throughput platform that minimizes data movement and enables fine-grained pipelining for future energy-constrained applications. $V_T$, $aJ$, and $G$-factors are used to quantify switching voltages, energies, and spin-transport properties throughout the modeling and design workflow.

Abstract

We demonstrate a non-volatile magnetoelectric magnonic memory (MEMM) that enables fully electrical write/read via direct magnon-driven sensing in an insulating antiferromagnet. A fabricated SrIrO3/La-BiFeO3/SrIrO3 trilayer exhibits sub-100 ps switching, a remnant polarization of 20 uC/cm2, and a readout voltage contrast close to 1mV between high and low-resistance states. To connect device physics to circuit behavior, we develop and experimentally validate a compact circuit model that captures spin Hall injection and spin transport. Simulations with optimized material parameters predict output voltages > 100mV, enabling cascading without external amplification. Using this framework, we design MEMM-based memory and logic blocks, including a 1T1R array, two inverter implementations (complementary two-device and single-device), and a three-input majority gate, and evaluate deep-pipelined operation. The model projects switching energies down to 1 aJ per operation and logic propagation delays of 30-60 ps, indicating MEMM as a promising platform for energy-constrained, high throughput computing.

Figures (9)

• Figure 1: Working principles of the trilayer MEMM device: (a) Device structure, composing of SO coupling layer, ME layer and interconnections; (b) Operating mechanism. The device state is defined as S=1 for the LRS and S=0 for the HRS; (c)The device operates in two modes: reading the stored state and writing a new state by applying switch voltages.
• Figure 2: (a) Schematic of a SrIrO$_3$ (SIO)/La-BiFeO$_3$ (LBFO)/SrIrO$_3$ (SIO) trilayer device and high resolution cross-sectional TEM image and vector polarization mapping. (b) Ferroelectric (polarization-electric field hysteresis) response of the LBFO from the SIO/LBFO/SIO trilayer. (c) The first harmonic lock-in measurement of output voltage $V_\text{ISHE}$ as a function of switch voltage.
• Figure 3: (a) An equivalent spin circuit model illustrating the processes from bottom to top: spin Hall effect, magnon transport, and inverse spin Hall effect. (b) Simplified circuit model showing control signal $V_G$, supply current $I_D$, and output voltage $V_o$. The equation on the right describes the relationship between output, control, and supply, where $\eta$ is a material-dependent parameter and $\alpha V_G^n$ is curve-fitted from the hysteresis loop, exhibiting a sharp increase near the threshold voltage $V_C$. (c) Equivalent small-signal circuit model. (d) Demonstrated device parameters and target values required to achieve output voltages of 100mV and above.
• Figure 4: (a) Comparison between simulation results and experimental data, extracted from the peak-to-peak voltage in the hysteresis loop. (b) Comparison of simulation results with previous studies huang_manipulating_2024 and our experimental data, revealing a consistent log-log relationship of voltage and spacing ($t_\text{SO}$, the thickness of top and bottom layer).
• Figure 5: Design space exploration for MEMM device optimization. (a) Output voltage contours as functions of spin Hall angles for the bottom ($\theta_{\text{SHE}}$) and top ($\theta_{\text{ISHE}}$) layers. (b) Output voltage contours as functions of electrical resistivities for the bottom ($\rho_{\text{SHE}}$) and top ($\rho_{\text{ISHE}}$) layers. (c) Impact of spin-orbit layer thicknesses ($t_{\text{SHE}}$, $t_{\text{ISHE}}$) on output voltage, illustrating scalability. (d) Output voltage as a function of magnetoelectric layer thickness ($t_{\text{BFO}}$). (e) Simulated switching energy from our model, demonstrating the potential for ultra‑low‑energy operation in the attojoule (1 aJ) range.