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Probabilistic approximate optimization using single-photon avalanche diode arrays

Ziyad Alsawidan, Abdelrahman S. Abdelrahman, Md Sakibur Sajal, Shuvro Chowdhury, Kai-Chun Lin, Hunter Guthrie, Sanjay Seshan, Shawn Blanton, Flaviano Morone, Marc Dandin, Kerem Y. Camsari, Tathagata Srimani

TL;DR

Results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.

Abstract

Combinatorial optimization problems are central to science and engineering and specialized hardware from quantum annealers to classical Ising machines are being actively developed to address them. These systems typically sample from a fixed energy landscape defined by the problem Hamiltonian encoding the discrete optimization problem. The recently introduced Probabilistic Approximate Optimization Algorithm (PAOA) takes a different approach: it treats the optimization landscape itself as variational, iteratively learning circuit parameters from samples. Here, we demonstrate PAOA on a 64$\times$64 perimeter-gated single-photon avalanche diode (pgSPAD) array fabricated in 0.35 $μ$m CMOS, the first realization of the algorithm using intrinsically stochastic nanodevices. Each p-bit exhibits a device-specific, asymmetric (Gompertz-type) activation function due to dark-count variability. Rather than calibrating devices to enforce a uniform symmetric (logistic/tanh) activation, PAOA learns around device variations, absorbing residual activation and other mismatches into the variational parameters. On canonical 26-spin Sherrington-Kirkpatrick instances, PAOA achieves high approximation ratios with $2p$ parameters ($p$ up to 17 layers), and pgSPAD-based inference closely tracks CPU simulations. These results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.

Probabilistic approximate optimization using single-photon avalanche diode arrays

TL;DR

Results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.

Abstract

Combinatorial optimization problems are central to science and engineering and specialized hardware from quantum annealers to classical Ising machines are being actively developed to address them. These systems typically sample from a fixed energy landscape defined by the problem Hamiltonian encoding the discrete optimization problem. The recently introduced Probabilistic Approximate Optimization Algorithm (PAOA) takes a different approach: it treats the optimization landscape itself as variational, iteratively learning circuit parameters from samples. Here, we demonstrate PAOA on a 6464 perimeter-gated single-photon avalanche diode (pgSPAD) array fabricated in 0.35 m CMOS, the first realization of the algorithm using intrinsically stochastic nanodevices. Each p-bit exhibits a device-specific, asymmetric (Gompertz-type) activation function due to dark-count variability. Rather than calibrating devices to enforce a uniform symmetric (logistic/tanh) activation, PAOA learns around device variations, absorbing residual activation and other mismatches into the variational parameters. On canonical 26-spin Sherrington-Kirkpatrick instances, PAOA achieves high approximation ratios with parameters ( up to 17 layers), and pgSPAD-based inference closely tracks CPU simulations. These results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.
Paper Structure (22 sections, 25 equations, 11 figures, 2 tables, 1 algorithm)

This paper contains 22 sections, 25 equations, 11 figures, 2 tables, 1 algorithm.

Figures (11)

  • Figure 1: PAOA implemented on pgSPAD-based probabilistic hardware. (a) Hardware--software loop: a classical optimizer updates PAOA variational parameters based on a cost computed from sampled configurations. (b) Die micrograph and device-level variability: Different pgSPADs exhibit distinct activation functions (pgSPAD 1 vs pgSPAD 2) due to fabrication-induced variation in dark-count statistics. Inset: cross-section of a perimeter-gated SPAD. (c) Printed circuit board hosting the $64 \times 64$ pgSPAD array with control and readout circuitry.
  • Figure 2: Operation and characterization of pgSPAD-based p-bits. (a) Cross-sectional schematic of a p+/n-well perimeter-gated SPAD. Higher gate voltage $V_g$ reduces the electric field at the junction edge, suppressing dark carrier generation and lowering the avalanche probability. (b) Functional block diagram. The device is biased above breakdown; an active quench-and-reset (AQAR) circuit detects avalanche events and re-arms the device. The binary output $m$ is assigned based on whether at least one avalanche occurs within the integration window. (c) Representative time traces of $m$ for three gate voltages, showing voltage-dependent switching statistics. (d) Measured activation functions for multiple pgSPAD devices, showing device-to-device variability in the sigmoidal response. Solid curve: fitted Gompertz function.
  • Figure 3: PAOA with symmetric and asymmetric activations benchmarking on 26-spin Sherrington--Kirkpatrick instances. (a,b) Residual energy and approximation ratio versus depth $p$ for PAOA (tanh–tanh): trained and evaluated with symmetric tanh activation (green), and PAOA (tanh–Gompertz): trained with tanh and evaluated with asymmetric Gompertz activation (red). PAOA schedules are trained on 30 instances and applied without retraining to 30 test instances. Each point averages $10^6$ independent runs. (c,d) Comparison of pgSPAD hardware inference (purple, 50 runs) and CPU simulation (red, $10^6$ runs), both using matched Gompertz-trained/Gompertz-inferred schedules. Hardware results closely track simulation despite reduced sampling and device-to-device variability. Error bars: 95% confidence intervals from bootstrap resampling.
  • Figure 4: Extrapolated PAOA performance at large depth. (a) Residual energy and (b) approximation ratio versus depth $p \in [10^2, 10^5]$ for PAOA (tanh--tanh) (green) and PAOA (tanh--Gompertz) (red), as defined in Fig. \ref{['fig:exp_paoa']}. Schedules learned at $p = 17$ are extrapolated without retraining. Each point averages 300 instances and $10^3$ runs. Error bars: 95% confidence intervals.
  • Figure S1: Cross-sectional view of a typical SPAD (a) and a pgSPAD (b).
  • ...and 6 more figures