Majority Boolean networks classifying density: structural characterization and complexity

TL;DR

This work investigates Density Classification on Majority Boolean Automata Networks (MBANs), where each node updates to the majority state among its in-neighbors. It provides a precise structural characterization of MBANs that solve DCT: a graph must avoid three forbidden patterns—leader, self-sufficient, and self-sufficient $m$-cycles—for any $m \ge 2$. The authors establish complexity results for recognizing these patterns: detecting a leader pattern is NP-complete, while detecting self-sufficient patterns (including maximal self-sufficient sets and self-sufficient cycles) is PSPACE-complete, with MBAN-LC (existence of a long limit cycle) also shown PSPACE-hard via reductions from iterated circuit value problems. Moreover, MBAN-DCT is shown to reside in PSPACE (with a conjecture that it is PSPACE-complete), and a PSPACE-hardness framework is built through monotone circuit simulations using majority gates. Together, these results illuminate when and how local majority dynamics on graphs can realize global density classification, and they map the computational barriers to recognizing the structural conditions that enable or obstruct such global coordination.

Abstract

Given a set of entities each holding a Boolean state, the Density Classification Task (DCT) asks them to converge to the most represented state. Given a directed graph of entities where each node synchronously updates to the local majority among its in-neighbors, we characterize in terms of three forbidden patterns when it solves DCT, and show that discovering these patterns is complete for NP and PSPACE.

Figures (7)

• Figure 1: Simulation of $\mathrm{AND}$ (left) and $\mathrm{OR}$ (right) gates of two Boolean inputs $x$ and $y$, where the top node applies a majority local rule equivalent to the simulated gate ($0$ and $1$ are constant Boolean values).
• Figure 2: Illustration of the construction of the digraph $G'$ of an MBAN (right), from a monotone circuit $C$ with $n=3$ and $|V_C|=8$ (left) in the proof of Theorem \ref{['th:config_converge_PSC']}. The $\wedge$ and $\vee$ labels in the nodes of $G'$ indicate the expected gate simulated when the state of $b_0$ is $0$ and the state of $b_1$ is $1$.
• Figure 3: Construction of $G'$ in the proof of Theorem \ref{['th:1_2_NPH']}. Arcs between the sets $X$, $V$ and $Y$ are labeled by the number of in-neighbors taken from the source set to all the vertices of the destination set. The total number of in-neighbors is given on the left, for each set and the distinguished vertex $x\in X$.
• Figure 4: Construction of $G'$ in the proof of Theorem \ref{['th:leader_NPC']}. Arcs between the sets $Y_i$ and $V$ are labeled by the number of arcs. All $X$ is in neighbor of all $Z'$. The sets $Y_i$ and $Z$ have all the vertices in $V'$ as in-neighbors, hence there cannot belong to $M(S)$ for any leader subset $S$.
• Figure 5: Effective construction of $L(C,x,i)$ in Definition \ref{['def:global_atractor']}. The test that the input is $1^{2n}$ is a circuit of depth $\log_2(2n)$ with at most $2n$$AND$ gates of fan-in two, and the test that $counter$ is not $0^n$ is analogous with $OR$ gates. Write $x$ is composed of $n$ NOT gates, $k$$AND$ gates (for the $0$s in $x$) and $n-k$$OR$ gates (for the $1$s in $x$). Add $1$ computes $counter + 1 \mod 2^n$ using $n$$XOR$ gates and $n$$AND$ gates. All the $OR$ and $AND$ gates drawn correspond to one gate per bit.

Theorems & Definitions (46)

• Theorem 3.2
• proof
• Definition 4.1
• Definition 4.2
• Lemma 4.3
• proof
• Definition 4.4
• Remark 1
• Lemma 4.5
• proof