Protection of Exponential Operation using Stabilizer Codes in the Early Fault Tolerance Era

TL;DR

This work proposes a systematic scheme to encode exponential operators of the form $\exp(-i\theta P)$ into small stabilizer codes with low overhead, aimed at reducing noise in non-Clifford operations during the EFTQC era. By ensuring the encoded operation matches the logical action and preserves the codespace, and by optimizing circuit structures to minimize first-order logical errors, the authors demonstrate substantial noise suppression across several small codes using postselection. Across the $[[n,n-2,2]]$ QEDC, the $[[5,1,3]]$, $[[7,1,3]]$, and $[[15,7,3]]$ codes, encoded circuits achieve 4–7x lower logical error rates than unencoded gates under current device noise, with acceptable discarding rates (often a few percent). The findings highlight that simple, postselected encoded implementations of exponential maps can meaningfully enhance EFTQC performance for both single- and multi-qubit rotations, especially as operator weight increases, and lay groundwork for practical comparisons with other fault-tolerance approaches.

Abstract

Quantum error correction offers a promising path to suppress errors in quantum processors, but the resources required to protect logical operations from noise, especially non-Clifford operations, pose a substantial challenge to achieve practical quantum advantage in the early fault-tolerant quantum computing (EFTQC) era. In this work, we develop a systematic scheme to encode exponential maps of the form $\exp(-iθP)$ into stabilizer codes with simple circuit structures and low qubit overhead. We provide encoded circuits with small first-order logical error rate after postselection for the [[n, n-2, 2]] quantum error-detecting codes and the [[5, 1, 3]], [[7, 1, 3]], and [[15, 7, 3]] quantum error-correcting codes. Detailed analysis shows that under the level of physical noise of current devices, our encoding scheme is 4--7 times less noisy than the unencoded operation, while at most 3% of runs need to be discarded.

Figures (8)

• Figure 1: CNOT ladder implementation of $\exp(-i\theta Z^{\otimes w}/2)$.
• Figure 2: Upper: an analog $X$ error can arise at location $b$. An $X$ error at location $a$ or $b$ is equivalent to an $X\otimes X$ error at locations $c_1, c_2$, and both will lead to the same logical error. Lower: an analog $Z$ error can arise at location $e$. A $Z$ error at location $d$ or $e$ and is equivalent to a $Z\otimes Z$ error at locations $f_1, f_2$, and both will lead to the same logical error. $\widetilde{\mathcal{U}}_{\rm rest}$ and $\widetilde{\mathcal{V}}_{\rm rest}$ represent all other noisy Clifford gates in the circuit.
• Figure 3: Two near-optimal encoded circuits for $\overline{R_{Y_{j}}(\theta)} = \exp(-i\theta Y_{j}X_{n-1}Z_{n}/2)$ in the $[[n, n-2, 2]]$ code. For clarity, only the relevant qubits are shown in the circuit diagrams.
• Figure 4: Encoded circuits for $\overline{\exp(-i\theta Z^{\otimes w}/2)}$ in the $[[n, n-2, 2]]$ code.
• Figure 5: Leading-order error rate for the near-optimal circuits we found for multi-qubit $Z$-operator rotations in the $[[n, n-2, 2]]$ code. Here, we plot the coefficient of $p$ in $p_L$. For the unencoded case, the $y$-axis shows $2(w-1)$. For encoded circuits, the $y$-axis shows $l/15$.

Theorems & Definitions (4)

• Proposition A.1: Sandwich by CNOTs
• proof
• Proposition A.2: Adding Ancilla
• proof