Presence versus absence of charging energies in PbTe quantum dots

TL;DR

This study resolves the long-standing ambiguity over charging energies in PbTe quantum dots by systematically reducing nanowire cross-sectional area, revealing a transition from no measurable $E_C$ at large areas to finite $E_C$ (up to $210\ \mu\mathrm{eV}$) as the dot size shrinks. It also demonstrates strong gate tunability: a redesigned top-gate architecture enables a flow from quantum-point-contact–ballistic transport to gate-defined quantum-dot behavior, supported by electrostatic simulations that quantify how dielectric screening and geometry determine the potential landscape. The work confirms that, despite PbTe’s huge dielectric constant, gate-defined QDs are feasible and controllable, offering a viable route to engineered PbTe-based quantum devices for Majorana and topological qubits. The combination of transport measurements across multiple dot sizes and complementary simulations provides practical guidance for designing tunable PbTe quantum devices with predictable charging energies and robust gate control.

Abstract

Charging energy ($E_C$) is essential in quantum dot (QD) devices. Previous studies on PbTe QDs have reported both the presence and absence of $E_C$. To resolve this ambiguity, we vary the QD size, i.e. the cross-sectional area of PbTe nanowires, and track the evolution of $E_C$. For large crosssectional areas ($\sim$ 16000 nm$^2$), the PbTe QDs exhibit no measurable $E_C$, while quantized levels are well resolved. Decreasing this area successively to 5000, 1500, and 500 nm$^2$, $E_C$ becomes finite and increases to 80, 160, and 210 $μ$eV, respectively. We further demonstrate the strong tunability of local gates, which can tune the PbTe device from the QD regime to the regime of ballistic transport. These results address concerns regarding the large dielectric constant of PbTe and provide key insights in engineering advanced PbTe quantum devices.

Figures (5)

• Figure 1: Schematics of QDs with and without $E_C$. (a) Energy diagram of a QD with $E_C$ = 0. $\delta$ denotes the level spacing due to quantum confinement. Arrows indicate spin orientations. (b) Conductance resonances and their evolution with magnetic field. The bias voltage is zero. (c-d) Schematics for the case with $E_C >$ 0.
• Figure 2: PbTe QD characteristics. (a-d) SEMs of four PbTe QDs. Scale bars are $300\nm$. (e-h) The corresponding cross-sectional STEMs. Scale bars are $100\nm$. Device B was burned after its measurement. We therefore show in (f) the STEM of an identical device from the same growth chip. They share the same wire width. The Al$_2$O$_3$ dielectric is labeled as AlO. (i-l) Charge stability diagrams of the four devices. $B = 0T$. The odd valleys are labeled as "o" and even valleys labeled as "e" in (k). (m-p) $B$ scans of QD states of the four devices. $V = 0\mV$. $B$ directions are labeled in (a-d): Out-of-plane for devices B, C, D and in-plane for device A. Odd valleys are labeled with green arrows.
• Figure 3: (a) Representative gate scan of a QD device without $E_C$ at $0T$ (black) and finite $B$ (red). The red curve is offset by 0.4$\times 2e^2/h$ for clarity. (b) Line cuts from Fig. 2(o) showing a finite $E_C$. The red curve is offset by 0.02$\times 2e^2/h$. $V = 0\mV$ for (a-b). (c) Extracted $E_C$ as a function of the cross-sectional area. This area includes the PbEuTe buffer and capping layers.
• Figure 4: Effects of local gates. (a) Pinch off curves of a QD device. The three gates were swept simultaneously. $B = 0T$. $V = 0.4\mV$ (red) and $0\mV$ (black). (b) Sweeping $V_{\text{PG}}$ while keeping $V_{\text{TG}}$ fixed at $0\V$, $-0.5\V$, $-1\V$, $-1.5\V$, and $-2\V$, respectively. (c) Schematic of the QD potential landscape in the QPC (left) and QD (right) regimes. $V = 0\mV$.
• Figure 5: Numerical simulations of the potential landscape. (a) Longitudinal schematic of the a PbTe QD. The scale bar is $100\nm$. PbTe and PbEuTe are both in light blue. Source (S) and drain (D) contacts and top gates are in yellow. (b) Potential energy ($-e\phi (x,y)$) of the region in (a) encircled by dashed lines. Note that the $y$-axis is enlarged for clarity. The nanowire segment corresponds to $y < 18\nm$ while the dielectric regions correspond to $y > 18\nm$. The boundary conditions are labeled (yellow lines), $V_{\text{S}}$ = $V_{\text{D}} = 0\V$, $V_{\text{TG1}}$ = $V_{\text{TG2}} = -2.2\V$, and $V_{\text{PG}} = 2.2\V$. (c) Distribution of the electric field $E(x,y)=-\nabla\phi(x,y)$. The arrow length indicates the field strength while its orientation is the field direction. The field strength in PbTe is so small and the arrows appear as dots. (d) Normalized electric field highlighting its direction. (e) Potential energy distribution at $\phi(x,y=9\nm)$ (the middle of PbTe). (f) The black curve is a replot of (e). The blue curve is the case of setting $V_{\text{TG1}}$ = $V_{\text{TG2}} = -0.2\V$, $V_{\text{PG}} = 0.2\V$. The red curve is the potential distribution by replacing PbTe with InAs. The gate settings are the same with the blue curve. (g) The black curve is a replot of (e). The blue curve corresponds to halving the thickness of the dielectric layer. The red curve corresponds to halving the PbTe thickness. The green curve corresponds to halving the width of the two tunnel gates. The gate settings remain the same with that in (b).