Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits

TL;DR

This work presents a wafer-scale packaging architecture capable of housing >500 superconducting qubits on a 3-inch die, engineered to suppress parasitic box modes, minimize packaging-related losses, and accommodate differential thermal contraction. Through finite-element loss budgeting, box-mode engineering with pillar metamaterials, and thermal-load simulations, the design is shown to be compatible with commercial dilution refrigerators. Experimental validation on 105/108 qubits across 12 multiplexing cells demonstrates a median coherence around $T_1\approx97~\mu$s$ and $T_{2e}\approx129~\mu$s, with readout fidelity near $97.5\%$ for 54 qubits and a median effective temperature of $36~\mathrm{mK}$. The results indicate that large-scale qubit integration can be achieved without compromising device performance and highlight the package as a powerful tool for high-throughput feedback on qubit performance across large sample sizes. Bootstrapping analyses further show how ensemble coherence measures stabilize with sub-samples, underscoring the value of large-N studies for manufacturing insights in quantum processors.

Abstract

Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes. We present a wafer-scale packaging architecture supporting over 500 qubits on a single 3-inch die. The package is engineered to suppress parasitic RF modes, and to mitigate material loss through simulation-informed design while managing differential thermal contraction to ensure robust operation at millikelvin temperatures. System-level heat-load calculations from a large wiring payload show this package may be operated in commercial dilution refrigerators. Measurements of the qubits loaded into the package show median $T_1$, $T_{2e} \sim 100~μ$s ($\sim$100 qubits) alongside readout with median fidelity of 97.5% (54 qubits) and a median qubit temperature of 36 mK (54 qubits). These results validate the performance of these packages and demonstrate that large-scale integration can be achieved without compromising device performance. Finally, we highlight the utility of these packages as a tool for high throughput feedback on qubit figures of merit over large sample sizes, allowing identification of performance outliers in the tails of the coherence distribution, a critical capability for informing fabrication and manufacture of high-quality quantum qubits and quantum processors.

Figures (7)

• Figure 1: Schematic showing the package. (a) A cross section of the part of the package showing the superconducting lid and base, a layered stack of PCB, superconducting spacer, wafer and the joints between the lid and base where pillars push into indium. The PCB is connected out-of-plane by SMPS connectorised coaxial cables. (b) Schematic layout of 56 triangular 9-1 multiplexing cells across a wafer. (c) A photograph of coaxmon qubits and resonators sitting on top of a spacer piece. Underneath the coaxial qubits and resonators the open-circuit output ports of the PCB are visible. Pillars from the base protrude through the full PCB/spacer/wafer stack. (d) Microwave lines connected to the multiplexing cell for control and readout of qubits.
• Figure 2: (a) Frequencies of RF modes of cylindrical cavities both bare and with pillars shorting the top and bottom faces. Alongside this we show the frequencies of transmon qubits measured in this work and their readout resonators which form two distinct frequency bands. (b - d) The electric field magnitude for different modes within the cylindrical cavity each holding 1 J of energy. (b) The 2.43 GHz fundamental mode of a cavity without pillars. (c) The 11.83 GHz fundamental mode of a cavity with pillars present as indicated by black dots. Here the electric field maxima occur towards the edge of the wafer. (d) A 14.02 GHz mode with substantial electric field strength within the forest of pillars showing a mode that extends into the pillars.
• Figure 3: Finite element simulations of participation ratios for different loss channels arising due to packaging materials. (a) Map of the package showing the qubit locations used in finite element simulations shown in panels (C-f). Grey circles indicate locations of pillars and coloured markers indicate qubits on different multiplexing cells. (b) A key indicating the markers used for individual qubits on a multiplexing cell. The results of loss simulations are shown in (c) conductor loss of the package walls (d) metal air dielectric loss of the package walls (e) seam loss from the side walls where package pieces join (f) seam loss from the pillar terminating in the package lid. Cross-section of the package showing (g) E-field and (h) H-field for an example simulation with the distance between the readout pin and the bottom of the monolithic wafer indicated. The E-field strengths are shown when 1 J of energy is stored in the mode. We simulate different participation ratios which vary with this distance including (i) metal air dielectric loss of the PCB metal surface (j) dielectric loss in the PCB bulk dielectric (k) the conductor loss from the exposed surface of the PCB. (c-d, j-k) Have a second y-axis indicating the Q factor limit from these loss channels which are determined using material loss-factors from literature values lei2023characterizationcalatroni2019cryogenicmazierska2005loss. (f, i) Do not include a second y-axis due to the lack of literature values governing these materials at relevant operating conditions.
• Figure 4: (a) Schematic showing the effects of differential thermal contraction upon cooling, where parts may collide with one another causing fine features to fail. The system is anchored on the left hand side (b) A birds-eye view of a pillar protruding through an apperture in a wafer showing the tolerancing of the aperture around a shunting pillar. We show the thermal contraction of (c) the Al base plate (d) the wafer (e) differential between (c) and (d) showing the relative travel of the pieces.
• Figure 5: Readout of 54 qubits. (a) Results from reading out one of the qubits showing 10k of the total 100k measured shots in the IQ plane. (b) shows the full data set projected onto the line of maximum state-discrimination. (c) A scatter plot showing the readout error from 54 qubits with optimised readout. We truncate the y axis for improved visibility but have overlap errors as small as $5\times10^{-7}\%$. A second linear y-axis is shown with the residual error (measurement - predicted). (d) A histogram of the effective temperatures of the same qubits extracted from the ground state histogram. Equivalent plots to (a) and (b) are shown for all qubits in the supplementary materials demonstrating that the results presented here are representative.