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Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories

Yousuf Choudhary, Tosiron Adegbija

TL;DR

AFMTJ memories offer picosecond switching but present sensing challenges due to low TMR, especially in densely integrated or thermally graded stacks. The authors propose a device–circuit co-design: STSA+ for thermally adaptive sensing, PD_EQ+ for tier-aware precharge/equalization, and WD_WRITE for asymmetric, low-energy write pulses, all validated on a calibrated AFMTJ SPICE model with 3D array parasitics. Across extensive PVT and Monte Carlo analyses, the proposed interfaces achieve robust read/write margins, sub-10^{-6} BER/WER, and near-ideal energy efficiency while preserving AFMTJ latency advantages. This work demonstrates that AFMTJ-based macros can be practical for high-density, latency-critical memory in future dense VLSI systems.

Abstract

Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.

Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories

TL;DR

AFMTJ memories offer picosecond switching but present sensing challenges due to low TMR, especially in densely integrated or thermally graded stacks. The authors propose a device–circuit co-design: STSA+ for thermally adaptive sensing, PD_EQ+ for tier-aware precharge/equalization, and WD_WRITE for asymmetric, low-energy write pulses, all validated on a calibrated AFMTJ SPICE model with 3D array parasitics. Across extensive PVT and Monte Carlo analyses, the proposed interfaces achieve robust read/write margins, sub-10^{-6} BER/WER, and near-ideal energy efficiency while preserving AFMTJ latency advantages. This work demonstrates that AFMTJ-based macros can be practical for high-density, latency-critical memory in future dense VLSI systems.

Abstract

Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.
Paper Structure (18 sections, 2 equations, 4 figures, 3 tables)

This paper contains 18 sections, 2 equations, 4 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background
  3. MTJ vs. AFMTJ: Device-Level Distinctions
  4. AFMTJ Device Model
  5. Baseline Sensing Architecture
  6. Write and Precharge Front-Ends
  7. 3D‑Integration and Parasitic Modeling
  8. Proposed Circuit Enhancements
  9. Adaptive Self-Timed Sense Amplifier (STSA+)
  10. PD_EQ+: Thermal‑Aware Precharge and Equalization Driver
  11. Asymmetric Write Driver
  12. Simulation Setup
  13. Results
  14. STSA vs. STSA+ Under PVT Variation
  15. Precharge/EQ Behavior Under Tier Temperature Gradients
  16. ...and 3 more sections

Figures (4)

  • Figure 1: High-level comparison of conventional MRAM peripheral circuits and the AFMTJ-specific interfaces proposed in this work. The enhanced peripherals introduce tunability, thermal awareness, and adaptive timing to address the low-TMR signal window, as well as the variation-induced sensing and write challenges present in AFMTJ arrays.
  • Figure 2: Peripheral circuits for AFMTJ sensing. (a) STSA+ augments a StrongARM latch with programmable offset injection, dynamic reference tracking, and temperature-aware $g_m$/tail-current biasing. (b) PD_EQ+ CMOS switch-level front-end for initializing the bitline (BL) prior to evaluation.
  • Figure 3: Write performance comparison of AFMTJ vs. MTJ across input voltages. Latency and energy include both the write and verify-read phases.
  • Figure 4: Monte Carlo transient waveforms for a 64$\times$64 AFMTJ tile under PVT variation. (a) Read path: output voltage $v_\mathrm{out}$ from STSA+. (b) Write path: free-layer magnetization $M_z$ under PD_EQ+ driving.