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FPGA Implementation of Sketched LiDAR for a 192 x 128 SPAD Image Sensor

Zhenya Zang, Mike Davies, Istvan Gyongy

TL;DR

This work tackles the data-rate bottleneck in high-resolution SPAD LiDAR by implementing a histogram-free online depth reconstruction using the SplineSketches algorithm on an FPGA. It employs fixed-point arithmetic and LUT-based polynomial spline evaluation to compute per-pixel sketches with $M=4$, achieving up to a $512\times$ compression compared with histogram outputs, and processes time stamps directly from a $192\times128$ SPAD array. Software simulations optimize LUT depth and FXP width, establishing that a LUT depth of 256 provides sub-bin accuracy while maintaining hardware efficiency. The FPGA design systematizes SPE-based on-the-fly sketch computation, with an effective frame-rate of about $12.7$ fps (from an original $6{,}500$ fps) and a maximum accumulation of $512$ frames, enabling scalable SPAD-based depth imaging. Real experiments validate online FPGA depth reconstruction against offline results, demonstrating high fidelity and confirming the approach's practicality while outlining paths for improvement via larger $M$ and external memory to further boost accuracy and throughput.

Abstract

This study presents an efficient field-programmable gate array (FPGA) implementation of a polynomial spline function-based statistical compression algorithm designed to address the critical challenge of massive data transfer bandwidth in emerging high-spatial-resolution single-photon avalanche diode (SPAD) arrays, where data rates can reach tens of gigabytes per second. In our experiments, the proposed hardware implementation achieves a compression ratio of 512x compared with conventional histogram-based outputs, with the potential for further improvement. The algorithm is first optimized in software using fixed-point (FXP) arithmetic and look-up tables (LUTs) to eliminate explicit additions, multiplications, and non-linear operations. This enables a careful balance between accuracy and hardware resource utilization. Guided by this trade-off analysis, online sketch processing elements (SPEs) are implemented on an FPGA to directly process time-stamp streams from the SPAD sensor. The implementation is validated using a customized LiDAR setup with a 192 x 128-pixel SPAD array. This work demonstrates histogram-free online depth reconstruction with high fidelity, effectively alleviating the time-stamp transfer bottleneck of SPAD arrays and offering scalability as pixel counts continue to increase for future SPADs.

FPGA Implementation of Sketched LiDAR for a 192 x 128 SPAD Image Sensor

TL;DR

This work tackles the data-rate bottleneck in high-resolution SPAD LiDAR by implementing a histogram-free online depth reconstruction using the SplineSketches algorithm on an FPGA. It employs fixed-point arithmetic and LUT-based polynomial spline evaluation to compute per-pixel sketches with , achieving up to a compression compared with histogram outputs, and processes time stamps directly from a SPAD array. Software simulations optimize LUT depth and FXP width, establishing that a LUT depth of 256 provides sub-bin accuracy while maintaining hardware efficiency. The FPGA design systematizes SPE-based on-the-fly sketch computation, with an effective frame-rate of about fps (from an original fps) and a maximum accumulation of frames, enabling scalable SPAD-based depth imaging. Real experiments validate online FPGA depth reconstruction against offline results, demonstrating high fidelity and confirming the approach's practicality while outlining paths for improvement via larger and external memory to further boost accuracy and throughput.

Abstract

This study presents an efficient field-programmable gate array (FPGA) implementation of a polynomial spline function-based statistical compression algorithm designed to address the critical challenge of massive data transfer bandwidth in emerging high-spatial-resolution single-photon avalanche diode (SPAD) arrays, where data rates can reach tens of gigabytes per second. In our experiments, the proposed hardware implementation achieves a compression ratio of 512x compared with conventional histogram-based outputs, with the potential for further improvement. The algorithm is first optimized in software using fixed-point (FXP) arithmetic and look-up tables (LUTs) to eliminate explicit additions, multiplications, and non-linear operations. This enables a careful balance between accuracy and hardware resource utilization. Guided by this trade-off analysis, online sketch processing elements (SPEs) are implemented on an FPGA to directly process time-stamp streams from the SPAD sensor. The implementation is validated using a customized LiDAR setup with a 192 x 128-pixel SPAD array. This work demonstrates histogram-free online depth reconstruction with high fidelity, effectively alleviating the time-stamp transfer bottleneck of SPAD arrays and offering scalability as pixel counts continue to increase for future SPADs.
Paper Structure (5 sections, 3 equations, 6 figures, 1 table)

This paper contains 5 sections, 3 equations, 6 figures, 1 table.

Table of Contents

  1. Introduction
  2. Algorithm Optimization for FPGA
  3. Software Simulation and Results
  4. FPGA Implementation
  5. Real Experiment

Figures (6)

  • Figure 1: Simulation results. Error maps of different LUT depths with $M=4$ and $p=1$, compared with FLP reference. The dataset is taken from altmann2016lidar.
  • Figure 2: Hardware architecture of SPEs implementation
  • Figure 3: LiDAR setup composed of the SPAD camera and Laser.
  • Figure 4: Optical calibration with a whiteboard placed 1 m in front of the sensor: (a) $\hat{z}$ from FPGA, (b) $\hat{z}$ from offline TCSPC histogram computation, and (c) their absolute difference.
  • Figure 5: Accuracy analysis with varying board distances by shifting the STOP signal: (a) IRFs for 15 measurements; (b) RMSE variations from online and offline sketches; (c,d) regression results versus the local CMM reference.
  • ...and 1 more figures