Fault Tolerant Design of IGZO-based Binary Search ADCs

TL;DR

This work tackles the reliability challenges of IGZO-based flexible electronics by developing a hierarchical fault-injection framework to quantify defect sensitivity in n-type Binary Search ADCs. It couples transistor-level defect models with system-level fault propagation, enabling analysis of single and multi-fault scenarios and guiding selective redundancy. The authors demonstrate substantial robustness gains—fault coverage rising from 60% to 92% for single faults and from 34% to 77.6% for multi-fault conditions—with only about 4–6% area and power overhead—by targeting critical early-stage components. The approach is validated on a 3-bit IGZO Binary Search ADC and is framed as generalizable to other unipolar FE technologies, offering a practical path to reliable, energy-efficient sensor interfaces in wearable and large-area systems.

Abstract

Thin-film technologies such as Indium Gallium Zinc Oxide (IGZO) enable Flexible Electronics (FE) for emerging applications in wearable sensing, personal health monitoring, and large-area systems. Analog-to-digital converters (ADCs) serve as critical sensor interfaces in these systems. Yet, their vulnerability to manufacturing defects remains poorly understood despite unipolar technologies' inherently high defect densities and process variations compared to mature CMOS technologies. We present a hierarchical fault injection framework to characterize defect sensitivity in Binary Search ADCs implemented in n-type only technologies. Our methodology combines transistor-level defect characterization with system-level fault propagation analysis, enabling efficient exploration of both single and multiple fault scenarios across the conversion hierarchy. The framework identifies critical fault-sensitive circuit components and enables selective redundancy strategies targeting only the most sensitive components. The resulting defect-tolerant designs improve fault coverage from 60% to 92% under single-fault injections and from 34% to 77.6% under multi-fault injection, while incurring only 4.2% area overhead and 6% power increase. While validated on IGZO-TFTs, the methodology applies to all emerging unipolar technologies.

Figures (5)

• Figure 1: (a) 3-bit Binary Search ADC conceptual architecture: cascaded comparators perform sequential decisions across three stages, producing binary output (D2, D1, D0) directly without digital encoding. (b) Comparator in IGZO-TFTs used for the Binary Search ADC. (c) Binary Search ADC architecture.
• Figure 2: Fault injection workflow: subcircuit fault characterization builds behavioral models used in system-level simulation to identify vulnerabilities, guiding targeted design hardening validated through multi-fault stress testing.
• Figure 3: Automated fault simulation infrastructure: Python framework coordinates netlist manipulation, parametric fault insertion, batch execution, and metric extraction to enable comprehensive robustness evaluation.
• Figure 4: Binary Search ADC fault sensitivity heat map under single-fault injection. Red: catastrophic; yellow: marginal; green: benign.
• Figure 5: Physical layout comparison: (a) baseline COM3 comparator (b) fault-resilient COM3 with extended redundancy (c) complete baseline 3-bit Binary Search ADC (d) fault-resilient design ECLR.