ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs

TL;DR

ACE-RTL introduces Agentic Context Evolution (ACE) to RTL code generation by fusing an RTL-specialized LLM with a frontier reasoning LLM via three interacting components: Generator, Reflector, and Coordinator. The Generator is trained on a large RTL dataset of 1.7 million specification–RTL pairs, the Reflector analyzes simulation feedback to propose fixes using a frontier model, and the Coordinator evolves context to guide subsequent generations. A parallel scaling strategy launches multiple ACE-RTL processes to drastically reduce convergence iterations. On the Comprehensive Verilog Design Problems (CVDP) benchmark, ACE-RTL achieves up to 44.87% improvement in pass rate over baselines and averages about four iterations to reach a correct RTL solution, demonstrating strong practical impact for complex RTL design tasks.

Abstract

Recent advances in large language models (LLMs) have sparked growing interest in applying them to hardware design automation, particularly for accurate RTL code generation. Prior efforts follow two largely independent paths: (i) training domain-adapted RTL models to internalize hardware semantics, (ii) developing agentic systems that leverage frontier generic LLMs guided by simulation feedback. However, these two paths exhibit complementary strengths and weaknesses. In this work, we present ACE-RTL that unifies both directions through Agentic Context Evolution (ACE). ACE-RTL integrates an RTL-specialized LLM, trained on a large-scale dataset of 1.7 million RTL samples, with a frontier reasoning LLM through three synergistic components: the generator, reflector, and coordinator. These components iteratively refine RTL code toward functional correctness. We further introduce a parallel scaling strategy that significantly reduces the number of iterations required to reach correct solutions. On the Comprehensive Verilog Design Problems (CVDP) benchmark, ACE-RTL achieves up to a 44.87% pass rate improvement over 14 competitive baselines while requiring only four iterations on average.

Figures (6)

• Figure 1: Comparison of prior works and ACE-RTL.
• Figure 2: Overview of ACE-RTL and its parallel scaling strategy.
• Figure 3: Case Study I --- RS232 Transmitter Module.
• Figure 4: Case Study II.
• Figure 5: Case Study III.