Focus Session: LLM4PQC -- An Agentic Framework for Accurate and Efficient Synthesis of PQC Cores

TL;DR

PQC hardware design is bottlenecked by translating reference C to synthesizable HLS and scaling NTT/FFT/sampling kernels. LLM4PQC introduces an agentic, feedback-driven workflow that extracts performance-critical subroutines, preprocesses C for HLS, generates HLS-C via C2HLSC, and verifies RTL through KATs, guided by a compile-simulate-synthesize loop. Case studies on Kyber, Dilithium, and Falcon demonstrate automated edges in design-space exploration and hardware synthesis, achieving competitive area metrics and proving the viability of an LLM-driven design loop, while highlighting latency trade-offs. The framework enables accelerated PQC accelerator development and provides a scalable path toward broader hardware-aware PQC deployment, with future work aiming at LLM specialization, RAG integration, and pre-synthesis PPA modeling.

Abstract

The design of post-quantum cryptography (PQC) hardware is a complex and hierarchical process with many challenges. A primary bottleneck is the conversion of PQC reference codes from C to high-level synthesis (HLS) specifications, which requires extensive manual refactoring [1]-[3]. Another bottleneck is the scalability of synthesis for complex PQC primitives, including number theoretic transform (NTT) accelerators and wide memory interfaces. While large language models (LLMs) have shown remarkable results for coding in general-purpose languages like Python, coding for hardware design is more challenging; feedback-driven and agentic integration are key principles of successful state-of-the-art approaches. Here, we propose LLM4PQC, an LLM-based agentic framework that refactors high-level PQC specifications and reference C codes into HLS-ready and synthesizable C code. Our framework generates and verifies the resulting RTL code. For correctness, we leverage a hierarchy of checks, covering fast C compilation and simulation as well as RTL simulation. Case studies on NIST PQC reference designs demonstrate a reduction in manual effort and accelerated design-space exploration compared to traditional flows. Overall, LLM4PQC provides a powerful and efficient pathway for synthesizing complex hardware accelerators.

Figures (1)

• Figure 1: The four phases of LLM4PQC: (i) PQC subroutine extraction, (ii) HLS preprocessing, (iii) HLS-C generation and DSE (based on integrating C2HLSC with Catapult), and (iv) synthesis and verification. Figure generated using NotebookLM.