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Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

Behdad Jamadi, Meysam Sohani Darban, Jeffrey S. Walling

Abstract

This paper presents a low-jitter hybrid voltage level shifter (HVLS) suitable for high-speed applications. The proposed architecture offers the advantage of cross-coupled feedback to simultaneously generate two voltage domain signals with available swings equal to the nominal supply and its double, which operate up to 12.4 GHz. A prototype HVLS circuit, along with impedance matching and a driver to enable high-speed off-chip testing, was fabricated in a 22-nm FD-SOI process technology. The prototype consumes a total die area, including the interface circuitry, of 477 x 462 um^2, while the active area of the level-shifter is 2 x 3.26 um^2. The average power consumption of the circuit is measured to be 4.43 uW per cycle, and the jitter is less than 150 fs-rms.

Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

Abstract

This paper presents a low-jitter hybrid voltage level shifter (HVLS) suitable for high-speed applications. The proposed architecture offers the advantage of cross-coupled feedback to simultaneously generate two voltage domain signals with available swings equal to the nominal supply and its double, which operate up to 12.4 GHz. A prototype HVLS circuit, along with impedance matching and a driver to enable high-speed off-chip testing, was fabricated in a 22-nm FD-SOI process technology. The prototype consumes a total die area, including the interface circuitry, of 477 x 462 um^2, while the active area of the level-shifter is 2 x 3.26 um^2. The average power consumption of the circuit is measured to be 4.43 uW per cycle, and the jitter is less than 150 fs-rms.
Paper Structure (12 sections, 15 equations, 20 figures, 1 table)

This paper contains 12 sections, 15 equations, 20 figures, 1 table.

Table of Contents

  1. Introduction
  2. Review of Voltage Level-Shifters (VLS)
  3. Delay Mismatch Effect On Output Power
  4. Case Study I: Ideal Cascode Class-D PA
  5. Case Study II: Non-Ideal Cascode Class-D PA
  6. Proposed Hybrid Voltage Level Shifter
  7. Function of HVLS for Analog and Digital Applications
  8. The Analog Application Simulation Results of the Proposed HVLS
  9. Digital Application Simulation Results of the Proposed HVLS.
  10. Measurement and Results
  11. Conclusion
  12. Acknowledgment

Figures (20)

  • Figure 1: SoC architectures: a) conventional SoC made of analog and digital blocks and b) modern digital SoC all blocks are made of digital gates.
  • Figure 2: Schematic of a) Type I: DCVS-based VLS; b) Type II: CM-based VLS; and c) WCMLS.
  • Figure 3: Maximum operation frequency of the three types of VLSs by adjusting the input voltage ($V_{DDL}$).
  • Figure 4: Propagation delay and power consumption of the three types of VLSs by adjusting input voltage.
  • Figure 5: Leakage current of of the three types of VLSs by adjusting their supply.
  • ...and 15 more figures