ALPHA-PIM: Analysis of Linear Algebraic Processing for High-Performance Graph Applications on a Real Processing-In-Memory System

TL;DR

This work addresses memory movement bottlenecks in large-scale graph processing by evaluating linear-algebraic graph primitives on a real-processing-in-memory system (UPMEM) with the ALPHA-PIM framework. It develops and compares SpMSpV- and SpMV-based kernels across multiple compressed formats and partitioning strategies, and introduces an adaptive runtime switching mechanism guided by a lightweight model to select the most efficient kernel based on input-vector sparsity. The study demonstrates substantial kernel and end-to-end speedups over CPU baselines and competitive gains versus SparseP, while revealing critical bottlenecks such as inter-DPU communication and memory-transfer overheads that inform hardware-software co-design for future PIM systems. The findings offer practical guidance for hardware designers on DPUs, memory hierarchies, and non-blocking DMA, and for software developers on partitioning and kernel selection strategies to accelerate memory-bound graph workloads in real PIM architectures.

Abstract

Processing large-scale graph datasets is computationally intensive and time-consuming. Processor-centric CPU and GPU architectures, commonly used for graph applications, often face bottlenecks caused by extensive data movement between the processor and memory units due to low data reuse. As a result, these applications are often memory-bound, limiting both performance and energy efficiency due to excessive data transfers. Processing-In-Memory (PIM) offers a promising approach to mitigate data movement bottlenecks by integrating computation directly within or near memory. Although several previous studies have introduced custom PIM proposals for graph processing, they do not leverage real-world PIM systems. This work aims to explore the capabilities and characteristics of common graph algorithms on a real-world PIM system to accelerate data-intensive graph workloads. To this end, we (1) implement representative graph algorithms on UPMEM's general-purpose PIM architecture; (2) characterize their performance and identify key bottlenecks; (3) compare results against CPU and GPU baselines; and (4) derive insights to guide future PIM hardware design. Our study underscores the importance of selecting optimal data partitioning strategies across PIM cores to maximize performance. Additionally, we identify critical hardware limitations in current PIM architectures and emphasize the need for future enhancements across computation, memory, and communication subsystems. Key opportunities for improvement include increasing instruction-level parallelism, developing improved DMA engines with non-blocking capabilities, and enabling direct interconnection networks among PIM cores to reduce data transfer overheads.

Figures (11)

• Figure 1: High-level organization of the UPMEM PIM system with a host CPU, DRAM main memory, and PIM-enabled memory (left), and a more detailed view of the UPMEM PIM chip (right) background-upmem.
• Figure 2: Execution time breakdown using 2048 DPUs and int32 data type for 1D/2D SpMV partitioning (normalized to 1D).
• Figure 3: Partitioning Strategies of Adjacency Matrix.
• Figure 4: Execution time per iteration on UPMEM for BFS and SSSP of two datasets using SpMV and SpMSpV.
• Figure 5: Execution time breakdown for SpMSpV variations using 2048 DPUs at input vector densities of $1\%$, $10\%$, and $50\%$ normalized to COO.