Surface code off-the-hook: diagonal syndrome-extraction scheduling

TL;DR

The paper tackles hook-error-induced distance loss in the rotated surface code by introducing a diagonal syndrome-extraction schedule that is globally uniform across all plaquettes of a given type. By aligning two-qubit gate orderings along the plaquette diagonals, diagonal hook errors cannot shortcut logical operators, preserving the full distance $d$ without geometry-dependent planning. Across memory, lattice-surgery primitives, spatial Hadamard operations with flags, and patch rotation, the diagonal schedule achieves at least comparable, often improved, logical error performance while reducing circuit-depth constraints, especially when measurements/resets can run in parallel with gates. The work also highlights decoder considerations, showing that Tesseract attains full distance with flags while matching-based decoders lag, and it proposes future directions for efficient decoding and extension to other codes and architectures.

Abstract

In the rotated surface code, hook errors (errors on auxiliary qubits midway through syndrome extraction that propagate to correlated two-qubit data errors) can reduce the circuit-level code distance by a factor of two if the extraction schedule is poorly chosen. The traditional approach uses N-shaped and Z-shaped schedules, selecting the orientation in each plaquette to avoid hook errors aligned with logical operators. However, this becomes increasingly complex within lattice surgery primitives with varied boundary geometries, and requires a 7-step schedule to avoid gate collisions. We propose the diagonal schedule, which orients hook errors along the diagonal of each plaquette. These diagonal errors crucially never align with logical operators regardless of boundary orientation, achieving full code distance. The diagonal schedule is globally uniform: all X-type plaquettes use one schedule and all Z-type plaquettes use another, eliminating geometry-dependent planning. On hardware supporting parallel measurement, reset, and gate operations, the schedule achieves a minimal period of 6 time steps, compared to 7 for the traditional approach. We demonstrate effectiveness for memory experiments, spatial junctions, spatial Hadamard gates, and patch rotation, showing equivalent or improved logical error rates while simplifying circuit construction.

Figures (8)

• Figure 1: Memory experiment comparison. (a) Traditional N/Z schedule for a memory experiment, with schedule orientations chosen based on boundary types (hook error orientations shown). (b) Diagonal schedule for the same memory experiment, using a globally uniform schedule (hook error orientations shown). (c) Z-shaped X-plaquette and N-shaped Z-plaquette circuits with their corresponding schedule diagrams. (d) Alternative orientation: N-shaped X-plaquette and Z-shaped Z-plaquette. (e) Diagonal X-plaquette and Z-plaquette circuits. (f) Logical error rate versus physical error rate for standard (dashed) and diagonal (solid) schedules at various code distances $d = 2k+1$. The two approaches achieve nearly identical logical error rates. Inset: effective distance $d_{\mathrm{eff}}$ (extracted by fitting the slope of $p_{\mathrm{logical}}$ vs. $p$ at low $p$) versus $k$, confirming $d_{\mathrm{eff}} \approx d = 2k+1$ for both schedules.
• Figure 2: L-shaped spatial junction.(a) Standard schedule with orientations chosen for the junction geometry. (b) Diagonal schedule using the globally uniform circuit. The diagonal schedule simplifies circuit construction while maintaining code distance.
• Figure 3: X-shaped spatial junction.(a) Standard schedule requiring careful orientation planning at the four-way junction. (b) Diagonal schedule with uniform circuits throughout. (c) Logical error rate comparison showing the diagonal schedule (solid) slightly outperforming the standard schedule (dashed). This improvement arises because the diagonal schedule enables a more compact period-6 circuit, while the standard schedule requires period-7 to avoid gate collisions at the junction. Inset: effective distance $d_{\mathrm{eff}}$ versus $k$, confirming $d_{\mathrm{eff}} \approx d = 2k+1$ for both schedules.
• Figure 4: Spatial Hadamard gate with the diagonal schedule. (a) Vertical orientation. (b) Horizontal orientation. (c) Detailed view of one of the stretched stabilizers and the corresponding syndrome extraction circuit. Circuits for the other stretched stabilizer are similar. Stretched stabilizers are prone to hook errors along their short direction. Flag measurements (shown in circuit) detect these problematic hook errors. (d) Logical error rate versus physical error rate using the Tesseract decoder. Different flag measurement settings are tested: "none" (dotted lines), "partial" (dashed lines), and "all" (solid lines). X-shaped markers at physical error rate $10^{-3}$ indicate the logical error rates achieved by the Tesseract decoder for a memory experiment occupying the same volume ($2\times 1\times 1$). With partial flags, the spatial Hadamard matches these logical error rates. Inset: effective distance $d_{\mathrm{eff}}$ versus $k$. The expected effective distances are achieved depending on the flag configuration.
• Figure 5: Patch rotation with the diagonal schedule. (a)--(d) Four time steps during the patch rotation circuit, showing how the patch geometry evolves. The diagonal schedule maintains its uniform structure throughout the rotation. (e) Logical error rate versus physical error rate. Different colors indicate different code distances $d = 2k+1$. Inset: effective distance $d_{\mathrm{eff}}$ versus $k$, confirming $d_{\mathrm{eff}} \approx d = 2k+1$.