Reconfigurable Low-Complexity Architecture for High Resolution Doppler Velocity Estimation in Integrated Sensing and Communication System

TL;DR

The paper tackles the Doppler resolution bottleneck in mmWave ISAC systems by proposing a reconfigurable, on-chip Doppler estimation architecture that combines FFT-based coarse estimation with ESPRIT-based fine estimation. It implements a hardware-software co-design on a Zynq MPSoC, including a low-complexity ESPRIT variant that reduces memory and multiplier requirements while preserving accuracy, and enables run-time reconfiguration via dynamic partial reconfiguration. The approach delivers up to 6.7× faster ESPRIT processing, up to 79% BRAM and 63% DSP reductions (compared with high-complexity ESPRIT/MUSIC), and up to 2× latency improvement through SNR-driven packet reduction, making it suitable for ISAC cycles that require fast Doppler discrimination of tightly spaced mobile users. The work demonstrates the practical viability of a reconfigurable DSP fabric for simultaneous sensing and communication, with potential extensions into deep-learning–augmented Doppler estimation to further enhance performance.

Abstract

In millimeter wave integrated sensing and communication (ISAC) systems for intelligent transportation, radar and communication share spectrum and hardware in a time division manner. Radar rapidly detects and localizes mobile users (MUs), after which communication proceeds through narrow beams identified by radar. Achieving fine Doppler resolution for MU clutter discrimination requires long coherent processing intervals, reducing communication time and throughput. To address this, we propose a reconfigurable architecture for Doppler estimation realized on a system on chip using hardware software codesign. The architecture supports algorithm level reconfiguration, dynamically switching between low-complexity, high-speed FFT-based coarse estimation and high complexity ESPRIT based fine estimation. We introduce modifications to ESPRIT that achieve 6.7 times faster execution while reducing memory and multiplier usage by 79% and 63%, respectively, compared to state of the art approaches, without compromising accuracy. Additionally, the reconfigurable architecture can switch to lower slow time packets under high SNR conditions, improving latency further by 2 times with no loss in performance.

Figures (8)

• Figure 1: (a) ISAC with TDM between radar and communication functionalities (b) ISAC system with BS supporting 3D RSP and multiple MUs
• Figure 2: (a) Hardware blocks in ESPRIT, detailed hardware architecture of pseudo inverse with (b) SVD, (c) Proposed low-complexity implementation, and (d) eigen value computation.
• Figure 3: Reconfigurable architecture for Doppler estimation via hardware software co-design on Zynq MPSoC
• Figure 4: Doppler velocity RMSE comparison between FFT and subspace algorithms for different numbers of packets under single target detection
• Figure 5: Doppler velocity RMSE with FFT and MUSIC for different Doppler precision with 100 packets