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Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study

Yousuf Choudhary, Tosiron Adegbija

TL;DR

Addresses the memory-wall by pursuing in-memory computing with AFMTJs, which offer picosecond switching and ultralow write energy. The authors build the first end-to-end SPICE framework for AFMTJs that models dual-sublattice dynamics via a compact $M_1$/$M_2$ formulation and validate it against experimental data. They demonstrate a hierarchical AFMTJ-based IMC architecture with bit-line computing, achieving approximately $17.5\times$ speedup and $20\times$ energy savings over a CPU baseline, outperforming MTJ-based IMC. The work establishes AFMTJs as a scalable, low-power primitive for ultrafast in-memory computing and provides a foundation for future hardware/software co-design in domains like edge AI and real-time signal processing.

Abstract

Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulation framework integrating multi-sublattice Landau-Lifshitz-Gilbert (LLG) dynamics with circuit-level modeling. SPICE-based simulations show that AFMTJs achieve ~8x lower write latency and ~9x lower write energy than conventional MTJs. When integrated into an in-memory computing architecture, AFMTJs deliver 17.5x average speedup and nearly 20x energy savings versus a CPU baseline-significantly outperforming MTJ-based IMC. These results establish AFMTJs as a compelling primitive for scalable, low-power computing.

Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study

TL;DR

Addresses the memory-wall by pursuing in-memory computing with AFMTJs, which offer picosecond switching and ultralow write energy. The authors build the first end-to-end SPICE framework for AFMTJs that models dual-sublattice dynamics via a compact / formulation and validate it against experimental data. They demonstrate a hierarchical AFMTJ-based IMC architecture with bit-line computing, achieving approximately speedup and energy savings over a CPU baseline, outperforming MTJ-based IMC. The work establishes AFMTJs as a scalable, low-power primitive for ultrafast in-memory computing and provides a foundation for future hardware/software co-design in domains like edge AI and real-time signal processing.

Abstract

Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulation framework integrating multi-sublattice Landau-Lifshitz-Gilbert (LLG) dynamics with circuit-level modeling. SPICE-based simulations show that AFMTJs achieve ~8x lower write latency and ~9x lower write energy than conventional MTJs. When integrated into an in-memory computing architecture, AFMTJs deliver 17.5x average speedup and nearly 20x energy savings versus a CPU baseline-significantly outperforming MTJ-based IMC. These results establish AFMTJs as a compelling primitive for scalable, low-power computing.
Paper Structure (11 sections, 1 equation, 4 figures, 2 tables)

This paper contains 11 sections, 1 equation, 4 figures, 2 tables.

Table of Contents

  1. Introduction
  2. AFMTJ Device Model
  3. Validation and Comparison
  4. AFMTJ-Based In-Memory Computing Architecture
  5. System Integration
  6. Cell Operations
  7. Evaluation
  8. Experimental Setup
  9. Device-Level Results
  10. System-Level Results
  11. Conclusion

Figures (4)

  • Figure 1: AFMTJ device structure. Each AFM layer contains two oppositely aligned sublattices coupled by inter-sublattice exchange ($J_{\text{AF}}$). Applied voltage drives spin-polarized current across the MgO barrier, enabling switching and readout.
  • Figure 2: High-level system architecture showing hierarchical AFMTJ-based in-memory compute. AFMTJ subarrays (C1--C6) serve as both memory (data) and compute (logic) blocks within L1, L2, and main memory, enabling processing in cache (PiC) and processing in memory (PiM).
  • Figure 3: Write (a) latency and (b) energy comparison of AFMTJ vs. MTJ across input voltages.
  • Figure 4: System-level (a) latency speedup and (b) energy savings of AFMTJ- and MTJ-based hierarchical IMC architecture versus the CPU baseline across workloads.