2.5D co-packaged optical I/O chipsets on a SiON/Si interposer for 4 $\times$ 100G optical interconnection

TL;DR

The paper tackles the need for scalable, energy-efficient chip-to-chip optical interconnects in AI/ML hardware. It proposes a 2.5D co-packaged architecture using a SiON/Si optical interposer that houses passive SiON routing and flip-chipped InP devices with CWDM functionality. The authors demonstrate all-on-chip I/O chipsets, integrating EML lasers, PDs, drivers, and TIAs, to achieve 4×100G PAM4 transmission over 2 km of SMF with polarization-insensitive reception. The results show clear eye diagrams and favorable BER performance without FEC, highlighting thermal management, fabrication tolerance, and scalable channel density as key advantages for future high-bandwidth interconnects.

Abstract

Optical I/O technologies have emerged as a potential industrial solution for high-performance data interconnection in AI/ML computing acceleration. While optical I/Os are deployed at the edge of computational chips by co-packaged optics (CPO), flexible and high-performance integration architectures need to be explored to address system-level challenges. In this work, we present and experimentally demonstrate a SiON/Si-based optical interposer that integrates high-bandwidth and energy-efficient optical I/O chipsets. High-performance photonic and electronic components are co-packaged on the interposer, leading to low-loss, signal-integrity-friendly, and thermally efficient characteristics. The optical interposer incorporates low-loss SiON photonic circuits to realize scalable waveguide routing and wavelength-division multiplexing (WDM) with polarization-insensitive operation and high fabrication tolerance, while supporting flip-chip integration with InP-based active devices, including electro-absorption modulated lasers (EMLs) and photodetectors (PDs). Based on this architecture, a 400-Gb/s single-fiber optical transceiver is implemented and experimentally evaluated. Clear eye diagrams and high receiver sensitivity demonstrate reliable high-speed data transmission, which offers scalable, high-bandwidth optical I/Os in future high-performance computational clusters.

Figures (8)

• Figure 1: Schematic illustration of the Optical I/O architecture based on TX/RX optical engines. (a) Data transmission between computational chips by SiON/Si optical engines; (b) Cross-sectional schematic photograph of co-packaged SiON/Si optical engines.
• Figure 2: Performance of MUX and DeMUX for O band CWDM. (a) Measured transmission spectrum of MUX; (b) Measured transmission spectrum of DeMUX. (c) The statistics of the central wavelength shift of 240 channels from 60 MUX devices after fabrication; (d) The statistics of central wavelength shift of 240 channels from 60 DeMUX devices after fabrication.
• Figure 3: Fiber coupler on the SiON/Si interposer for SMFs. (a) Microscope pictures; (b) Measured optical mode field; (c) Measured transmission spectra under TE and TM polarizations; (d) Measured insert loss of six different samples at 1310 nm.
• Figure 4: The operation performance of four flip-chip bonded EMLs under 50℃. (a) Measured spectra of four CWDM EMLs; (b) Measured I-V curves of four CWDM EMLs; (c) Measured optical power curves at the edge of transmitter chip; (d) Measured modulated optical power curves at the edge of transmitter chip.
• Figure 5: Statistics of flip-chip bonded III-V devices. (a)The change of laser threshold current after 2000 hours of operation under 50 mA and 40℃. The dark current (b) and responsiveness (c) of PDs under 25℃ and 75℃.