Magnetic Field-Mediated Superconducting Logic

TL;DR

This work presents SuperMag, a non-volatile superconducting logic paradigm in which a spin-orbit torque–switched ferromagnet proximity-couples to a superconductor to control its state. By combining an external bias field with the proximity magnetization, the SuperMag switch toggles between zero and high resistance, enabling direct cascadable, clockless logic with non-volatile states. The authors demonstrate a working Al/MgO/CoFeB implementation and outline a complete SuperMag logic/memory family (inverter, NAND, transmission gates, full adder, nvRAM), arguing for substantial gains in energy efficiency and scalability over CMOS and RSFQ under material optimization. System-level analyses indicate dramatic improvements in area and energy-delay products with future material advances, positioning SuperMag as a promising path toward ultra-efficient superconducting computing across cryogenic and possibly room-temperature regimes.

Abstract

While superconductors are highly attractive for energy-efficient computing, fundamental limitations in their logic circuit integration have hindered scaling and led to increased energy consumption. We therefore propose and experimentally demonstrate a novel superconducting switching device utilizing the proximity magnetization from a spin-orbit torque-switched magnet to control the resistivity of a superconductor. We further propose a complete logic family comprised solely of these devices. This novel implementation has the potential to drastically outperform existing superconducting logic families in terms of energy efficiency and scalability.

Figures (17)

• Figure 1: SuperMag switch. a) A current pulse through the SOT layer (blue rectangle), from bottom right to top left, switches the magnet's (green disk) magnetization to the right via the spin-Hall effect. b) Passing a current from top left to bottom right switches the magnetization to the left. c) In the presence of a biasing field (purple arrows) and proximity coupled field from the magnet through an insulating layer (thin yellow disk), there is a sufficient magnetic field to cause the superconducting wire to be in a high resistance state. d) When the proximity coupled field of the magnet opposes the bias field such that only a small field is felt by the superconductor, the superconductor is in a zero resistance state. e) Truth table for the SuperMag switch. f) SuperMag switch schematic symbol. Current flowing in the same (opposite) direction of the triangle closes (opens) switch $\alpha$.
• Figure 2: a) Fabricated Al/MgO/CoFeB device. b) Cross sectional illustration of device. B$_\textnormal{ext}$ is the in-plane external magnetic field, M$_\textnormal{FM}$ is the ferromagnet magnetization, B$_\textnormal{prox}$ is the effective field due to proximity effects felt by the superconductor. c) (solid red) The experimentally measured resistance of the Al as a function of B$_\textnormal{ext}$ and M$_\textnormal{FM}$ at 270 mK. d) State variables of experiment through time. R$_\textnormal{SC}$ is the field-modulated resistance of the superconductor. Dashed lines in the B$_\textnormal{ext}$ (B$_\textnormal{ext} + \textnormal{B}_\textnormal{prox}$) column correspond with the switching threshold magnetic field of the ferromagnet (superconductor).
• Figure 3: a-d) Complementary SuperMag inverter/buffer. a) 3D view. The upstream logic drives the SOT layers of the SuperMag switches via the switching wire (blue). The resistance of the output wire (green) is mediated by the magnetic state of the switches. b) SuperMag inverter schematic. Throughout this work the color blue is used for circuit or switch inputs and switching wires and green for output wires and outputs in general. A SuperMag buffer may be formed by swapping the $V^+$ and $V^-$ terminals. c) CMOS inverter. d) SuperMag inverter truth table. Bold, underlined "0 $\Omega$"s indicate zero-resistance paths contributing to I$_\textnormal{out}$. e-g) Complementary SuperMag NAND gate. e) SuperMag NAND schematic. f) CMOS NAND gate. g) SuperMag NAND gate truth table.
• Figure 4: SuperMag one-bit full adder circuit structure and truth tables. a) The full adder comprises two SuperMag XOR gates (left, similar to Supp. Fig. \ref{['fig:xor']}) and one AO22 gate (right). Cascade is accomplished by using the output of the upper-left XOR, X, to drive switching wires of both of the other gates. Fanout is accomplished by chaining the SuperMag switches connected to A, B, and X in series. b-d) Truth tables of the computation of X, SUM, and Cout respectively. The S$_\textnormal{A}$, S$_\textnormal{B}$, S$_\textnormal{X}$, and S$_\textnormal{Cin}$ columns of (c) indicate the 'on' branch of the corresponding complementary SuperMag switch pairs of (a).
• Figure 5: nvRAM with SuperMag. a) RAM bit cell and truth table. Cell state is stored in SuperMag switches $\gamma$ and $\delta$, and read at node V$_\textnormal{cell}$. If a '1' ('0') is stored, V$_\textnormal{cell}$ is driven to V$^+$ (V$^-$). Writing is performed by driving WWL high and asserting BL with the bit to be written (V$^+$ or V$^-$). The write access switch connects BL to the switching wires of switches $\delta$ and $\gamma$, overwriting the cell state. To read, RWL is driven high, connecting V$_\textnormal{cell}$ to BL. b) nvRAM array comprising multiple bit cells. c) Write and read drivers for column 1 of the nvRAM. Writing involves sending logic '1' to Wr_En and activating the chosen WWL, followed by asserting D$_1$ with the data to be written. Reading is performed by activating Rd_En and one RWL to select a word. The V$_\textnormal{cell}$ values of that word will drive the BLs and overwrite the the read driver buffers, which will latch the output data, thereby completing the read operation.